Voltage-aware static timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 2156-2169

  Kouroossis, Dionysios ^a,b   Ahmadi, Rubil ^a,b,c   Najm, Farid N ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

Power grid; Rail voltage variations; Static timing analysis; Verification tools

Indexed keywords

POWER GRID; RAIL VOLTAGE VARIATIONS; STATIC TIMING ANALYSIS (STA); VERIFICATION TOOLS;

DELAY CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GATES (TRANSISTOR); OPTIMIZATION; PROBLEM SOLVING; TIME DOMAIN ANALYSIS;

TIMING CIRCUITS;

EID: 33748288303     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.860953     Document Type: Article

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