ECO algorithms for removing overlaps between power rails and signal wires

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 67-74

  Xiang, Hua ^a   Chao, Kai Yuan ^b   Wong, D F ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

POWER RAILS; SIGNAL WIRES;

ELECTRONICS PACKAGING; MARKETING; PERFORMANCE; RELIABILITY; ROUTERS; VLSI CIRCUITS;

ALGORITHMS;

EID: 0036911942     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774582     Document Type: Conference Paper

References (5)

1. T.E. Dillinger, VLSI Engineering, Prentice Hall, 1988.
2. F. Mo, A. Tabbara, and R.K. Brayton, "A Force-Directed Macro-Cell Placer," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2000.
3. S. Nag and K. Chaudhary, "Post-Placement Residual-Overlap Removal with Minimal Movement," Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 1999.
4. N. Quinn and M.A. Breuer, "A Forced Directed Component Placement Procedure for Printed Circuit Boards," IEEE Transactions on Circuits and Systems, 1979.
5. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993.