Asymmetric tunneling source mosfets: A novel device solution for sub-100nm CMOS technology

International Journal of High Speed Electronics and Systems

Volumn 16, Issue 1, 2006, Pages 95-102

  Girish, N V ^a   Jhaveri, Ritesh ^b   Woo, J C S ^a,b  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

MOSFET; Nanotransistor

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON TUNNELING; NANOSTRUCTURED MATERIALS; TRANSISTORS;

MOSFET; NANOTRANSISTORS;

MOSFET DEVICES;

EID: 33747668151     PISSN: 01291564     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0129156406003552     Document Type: Conference Paper

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