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Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 590-593

Figaro - An automatic tool flow for designs with dynamic reconfiguration

(4) Nasi, Kelly a Karoubalis, Theodore a Daněk, Martin b Pohl, Zdeněk b

a Applications and RandD (Greece)

b INSTITUTE OF INFORMATION THEORY AND AUTOMATION (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER AIDED DESIGN; COMPUTER NETWORKS; FIELD PROGRAMMABLE GATE ARRAYS; NETWORK PROTOCOLS; STANDARDS;

AUTOMATIC TOOL FLOW; BITSTREAM GENERATION; DYNAMIC RECONFIGURATION; USER-SPECIFIED RECONFIGURATION;

COMPUTER ARCHITECTURE;

EID: 33746930862 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/FPL.2005.1515792 Document Type: Conference Paper

Times cited : (5)

References (8)

1
- 0036054393
- Dynamic hardware plugins in an FPGA with partial runtime reconfiguration
- B. Ackland, Ed. ACM Press
- E. L. Horta, J. W. Lockwood, and D. Parlour, "Dynamic hardware plugins in an FPGA with partial runtime reconfiguration," in Proceedings of the 39th Design Automation Conference, B. Ackland, Ed. ACM Press, 2002, pp. 343-348.
- (2002) Proceedings of the 39th Design Automation Conference , pp. 343-348
- Horta, E.L.¹ Lockwood, J.W.² Parlour, D.³

2
- 22444431905
- Xilinx
- Xilinx Application Note 290 - Two flows for partial reconfiguration: Module based and Difference based. Xilinx, 2004.
- (2004) Xilinx Application Note 290 - Two Flows for Partial Reconfiguration: Module Based and Difference Based

3
- 0036385195
- Timing verification of dynamically reconfigurable logic for the Xilinx Virtex FPGA series
- M. Schlag and S. Trimberger, Eds. ACM Press
- I. Robertson, J. Irvine, P. Lysaght, and D. Robinson, "Timing verification of dynamically reconfigurable logic for the Xilinx Virtex FPGA series." in Proceedings of the 10th International Symposium on Field-Programmable Gate Arrays, M. Schlag and S. Trimberger, Eds. ACM Press, 2002, pp. 127-132.
- (2002) Proceedings of the 10th International Symposium on Field-programmable Gate Arrays , pp. 127-132
- Robertson, I.¹ Irvine, J.² Lysaght, P.³ Robinson, D.⁴

4
- 0032097108
- Improving functional density using run-time circuit reconfiguration
- Feb.
- M. J. Wirthlin and B. L. Hutchings, "Improving functional density using run-time circuit reconfiguration," IEEE Trans. VLSI Syst., vol. 6, no. 2, pp. 247-256, Feb. 2002.
- (2002) IEEE Trans. VLSI Syst. , vol.6 , Issue.2 , pp. 247-256
- Wirthlin, M.J.¹ Hutchings, B.L.²

5
- 33746878746
- Atmel
- AT94K - 5K to 40K Gates of AT40K FPGA with 8-bit AVR Microcontroller. Atmel, 2002.
- (2002) AT94K - 5K to 40K Gates of AT40K FPGA with 8-bit AVR Microcontroller

6
- 33746900694
- Atmel
- AT40K Series Cache Logic Configuration. Atmel, 1998.
- (1998) AT40K Series Cache Logic Configuration

7
- 79955136190
- High-level partitioning of digital systems based on dynamically reconfigurable devices
- M. Glesner, P. Zipf, and M. Renovell, Eds. Springer
- R. Kielblik, J. M. Moreno, A. Napieralski, G. Jablonski, and T. Szymanski, "High-level partitioning of digital systems based on dynamically reconfigurable devices." in Proceedings of the 12th International Conference on Field-Programmable Logic and Applications, M. Glesner, P. Zipf, and M. Renovell, Eds. Springer, 2002, pp. 271-280.
- (2002) Proceedings of the 12th International Conference on Field-programmable Logic and Applications , pp. 271-280
- Kielblik, R.¹ Moreno, J.M.² Napieralski, A.³ Jablonski, G.⁴ Szymanski, T.⁵

8
- 33746884199
- The RECONF2 consorcium
- The RECONF2 project web page -http://reconf.org. The RECONF2 consorcium, 2002.
- (2002) The RECONF2 Project Web Page

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