High-level partitioning of digital systems based on dynamically reconfigurable devices

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 271-280

  Kielbik, Rafal ^a   Moreno, Juan Manuel ^b   Napieralski, Andrzej ^a   Jablonski, Grzegorz ^a   Szymanski, Tomasz ^a  

^a LODZ UNIVERSITY OF TECHNOLOGY   (Poland)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SYSTEM; HYPEREDGES; HYPERGRAPH; RECONFIGURABLE DEVICES; TEMPORAL PARTITIONING; TIME DEPENDENCY; VHDL DESCRIPTION;

ALGORITHMS; COMPUTER HARDWARE; DIGITAL DEVICES;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 79955136190     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (13)

1. de Micheli, G.: Synthesis and Optimisation of Digital Circuits. McGraw-Hill, 1994
2. Canto, E., Moreno, J.M., Cabestany, J., Lacadena, I., Insenser, J.M.: A Temporal Bipartitioning Algorithm for Dynamically Reconfigurable FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 9, No. 1., pp. 210-218, February 2001 (Pubitemid 32922827)
3. Canto, E.: Temporal Bipartitioning Techniques for Multi-context FPGAs. Ph.D. Thesis, Universitat Politecnica de Catalunya, July 2001
4. Kaul, M., Vemuri, R.: Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. Proceedings on Design, Automation and Test in Europe (DATE'99), IEEE Computer Society Press, pp. 202-209, March 1999
5. Maestre, R., Kurdahi, F.J., Fernandes, M., Hermida, R., Bagherzadeh, N., Singh, H.: A Framework for Reconfigurable Computing: Task Scheduling and Context Management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 858-873, December 2001 (Pubitemid 34126217)
6. Bhat, N.B., Chaudhary, K., Kuh, E.S.: Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device. UCB/ERL M93/42, University of California, Berkley, June 1993
7. DeHon, A.: Reconfigurable Architectures for General-Purpose Computing. Ph.D. Thesis, Massachusetts Institute of Technology, October 1996
8. Trimberger, S.: A Time Multiplexed FPGA. Proceedings FPGAs for Custom Computing Machines (FCCM'97), IEEE Computer Society, 1997
9. Faura, J., Horton, C., van Doung, P., Madrenas, J., Insenser, J.M.: A Novel Mixed Signal Programmable Device with On-Chip Microprocessor. Proceedings of the IEEE 1997 Custom Integrated Circuits Conference, pp.103-106
10. Faura, J., Moreno, J.M., Aguirre, M-A., van Doung, P., Insenser, J.M.: FIPSOC: A Filed Programmable System On a Chip. Proceedings of the XII Design of Circuits and Integrated Systems Conference (DCIS'97), pp. 597-602, Sevilla, November 1997
11. Fiduccia, C.M., Mattheyses, R.M.: A Linear-Time Heuristic Procedure for Improved Network Partitions. Proceedings on Design Automation Conference, pp. 241-247, 1982
12. Enzler, R., Jeger, T., Cottet, D., Tröster, G.: High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs. Proceedings of FPL 2000, pp. 525-534, Springer-Verlag, 2000
13. Machado, F., Torroja, Y., Casado, F., Riesgo, T., de la Torre, E., Uceda, J.: A Simple Method to Estimate the Area of VHDL RTL descriptions. Proceedings of the XV Design of Circuits and Integrated Systems Conference (DCIS 2000), Montpellier, November 2000