Measurement of the switching activity of CMOS digital circuits at the gate level

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2451, Issue , 2002, Pages 353-362

  Baena, C ^a   Juan Chico, J ^a   Bellido, M J ^a   Ruiz de Clavijo, P ^a   Jimenez C J ^a   Valencia, M ^a  

^a UNIVERSITY OF SEVILLE   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; SIMULATORS; SWITCHING; TIMING CIRCUITS;

ACCURATE ESTIMATION; CMOS DIGITAL CIRCUITS; DELAY MODELING; GATE LEVELS; PARASITIC EFFECT; SWITCHING ACTIVITIES;

COMPUTER CIRCUITS;

EID: 33746869222     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45716-x_35     Document Type: Conference Paper

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