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Volumn 1, Issue 3-4, 2005, Pages 165-178

Online placement for dynamically reconfigurable devices

Author keywords

FPGA; hardware operating systems; reconfigurable computing; temporal placement

Indexed keywords


EID: 33746863976     PISSN: 17411068     EISSN: 17411076     Source Type: Journal    
DOI: 10.1504/ijes.2005.009947     Document Type: Article
Times cited : (9)

References (16)
  • 2
    • 12444285805 scopus 로고    scopus 로고
    • A new approach for online placement on reconfigurable devices
    • Reconfigurable Architectures Workshop (RAW-2004), IEEE-CS Press, Santa Fe NM, USA, 26-27 April
    • Ahmadinia, A., Bobda, C. and Teich, J. (2004) ‘A new approach for online placement on reconfigurable devices’, Proc. of the International Parallel and Distributed Processing Symposium (IPDPS-2004), Reconfigurable Architectures Workshop (RAW-2004), IEEE-CS Press, Santa Fe NM, USA, 26-27 April, p.134a.
    • (2004) Proc. of the International Parallel and Distributed Processing Symposium (IPDPS-2004) , pp. 134a
    • Ahmadinia, A.1    Bobda, C.2    Teich, J.3
  • 6
    • 84955597352 scopus 로고    scopus 로고
    • A virtual hardware operating system for the Xilinx XC6200
    • Darmstadt, Germany, 23-25 September
    • Brebner, G. (1996) ‘A virtual hardware operating system for the Xilinx XC6200’, Proceedings of 6th International Workshop on Field-Programmable Logic, Darmstadt, Germany, 23-25 September, pp.327–336.
    • (1996) Proceedings of 6th International Workshop on Field-Programmable Logic , pp. 327-336
    • Brebner, G.1
  • 8
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: on-chip interconnection networks
    • Las Vegas, NV, June
    • Dally, W.J. and Towles, B. (2001) ‘Route packets, not wires: on-chip interconnection networks’, Proceedings of the Design Automation Conference, Las Vegas, NV, June, pp.684–689.
    • (2001) Proceedings of the Design Automation Conference , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 11
    • 0347117076 scopus 로고    scopus 로고
    • Optimal FPGA module placement with temporal precedence constraints
    • IEEE-CS Press
    • Fekete, S., Köhler, E. and Teich, J. (2001) ‘Optimal FPGA module placement with temporal precedence constraints’, Proc. of Design Automation and Test in Europe, IEEE-CS Press, pp.658–665.
    • (2001) Proc. of Design Automation and Test in Europe , pp. 658-665
    • Fekete, S.1    Köhler, E.2    Teich, J.3
  • 14
    • 84949687270 scopus 로고    scopus 로고
    • Xilinx Inc. http://www.xilinx.com.
  • 15
    • 84949687271 scopus 로고    scopus 로고
    • A network is strongly connected, if for each pair of network elements a path exists which connects the two elements
    • A network is strongly connected, if for each pair of network elements a path exists which connects the two elements.
  • 16
    • 84949687272 scopus 로고    scopus 로고
    • The neighbour-routers of the routers around the chips are assumed to be the package pins through which external modules can access the network
    • The neighbour-routers of the routers around the chips are assumed to be the package pins through which external modules can access the network.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.