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Volumn 1, Issue , 2005, Pages 826-829

An adaptive bandwidth phase locked loop with locking status indicator

Author keywords

Fast locking; Locking status indicator; Loop bandwidth; Low jitter; Phase locked loop; Schmitt trigger

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FREQUENCIES; JITTER; TRIGGER CIRCUITS;

EID: 33746168711     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/KORUS.2005.1507914     Document Type: Conference Paper
Times cited : (15)

References (6)
  • 1
    • 0029254070 scopus 로고
    • A 0.18um CMOS hot-standby phase-locked loop using a noise immune adaptive-gain voltage-controlled oscillator
    • Feb
    • M. Mizuno et al., "A 0.18um CMOS hot-standby phase-locked loop using a noise immune adaptive-gain voltage-controlled oscillator," ISSCC Dig. Tech. Papers, pp. 268-269, Feb, 1995 G.
    • (1995) ISSCC Dig. Tech. Papers , pp. 268-269
    • Mizuno, M.1
  • 2
    • 0031233489 scopus 로고    scopus 로고
    • An optimum phase-acquisition technique for charge-pump phase-locked loops
    • Sept.
    • Roh, Y. Lee, and B. Kim, "An optimum phase-acquisition technique for charge-pump phase-locked loops," IEEE Trans. Circuit Syst.II, vol. 44, pp. 729-740, Sept. 1997
    • (1997) IEEE Trans. Circuit Syst.II , vol.44 , pp. 729-740
    • Roh, Y.L.1    Kim, B.2
  • 3
    • 0034298112 scopus 로고    scopus 로고
    • Fast-switching frequency. Synthesizer with a discriminator-aided phase detector
    • October
    • Ching-Yuan Yang and Shen-Iuan Liu, "Fast-Switching Frequency. Synthesizer with a Discriminator-Aided Phase Detector," IEEE J, Solid-State Circuits, vol. 35, No. 10, October 2000
    • (2000) IEEE J, Solid-state Circuits , vol.35 , Issue.10
    • Yang, C.-Y.1    Liu, S.-I.2
  • 4
    • 0034248698 scopus 로고    scopus 로고
    • A low-noise fast lock phase locked loop with adaptive bandwidth control
    • Aug.
    • Joonsuk Lee, and Beomsup Kim, "A Low-Noise Fast Lock Phase Locked Loop with Adaptive Bandwidth Control," IEEE J, Solid-State Circuits, vol. 35, pp.1137-1145, Aug. 2000
    • (2000) IEEE J, Solid-state Circuits , vol.35 , pp. 1137-1145
    • Lee, J.1    Kim, B.2
  • 5
    • 0001036352 scopus 로고    scopus 로고
    • An adaptive PLL tuning system architecture combining high spectral purity and fast settling time
    • April
    • Cicero S. Vaucher, "An Adaptive PLL Tuning system Architecture Combining High Spectral Purity and Fast Settling Time," IEEE J, Solid-State Circuits, vol. 35, No. 4, April 2000
    • (2000) IEEE J, Solid-state Circuits , vol.35 , Issue.4
    • Vaucher, C.S.1
  • 6
    • 0038380469 scopus 로고    scopus 로고
    • A stabilization technique for phase-locked frequency synthesizers
    • June
    • Tai-Cheng Lee and Behzad Razavi, " A Stabilization Technique for Phase-Locked Frequency Synthesizers," IEEE J, Solid-State Circuits, vol. 38, No. 6, June 2003
    • (2003) IEEE J, Solid-state Circuits , vol.38 , Issue.6
    • Lee, T.-C.1    Razavi, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.