Optimum phase-acquisition technique for charge-pump PLL

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 9, 1997, Pages 729-740

  Roh, Gyoung Tae ^a   Lee, Yong Hoon ^a   Kim, Beomsup ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Charge pump pll (cp pll); Gear shifting; Mmse criterion, optimum sequence; Phase acquisition; Zero phase start (zps)

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DATA COMMUNICATION EQUIPMENT; DIFFERENCE EQUATIONS; GAIN CONTROL;

INPUT PHASE JITTER; PHASE ACQUISITION ALGORITHM; ZERO PHASE START;

PHASE LOCKED LOOPS;

EID: 0031233489     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.625005     Document Type: Article

References (33)

1. T. H. Lee and J. F. Bulzacchelli A 155-MHz clock recovery delayand phase-locked loop," IEEE J. Solid-State Circuits, vol. 27, pp. 1736-1746, Dec. 1992.
2. B. Kim, J. D. Greco, H. C. Yang, W. S. Wu, and R. F. Chowdhury An integrated CMOS mixed-mode signal processor for disk drive read channel applications," IEEE Trans. Circuits Syst., vol. 41, pp. 1-18, Jan. 1994.
3. B. Kirn, J. D. Greco, D. Helman, H. Yang, S. Wu, and R. Chowdhury A high speed digital data separator design using real time DSP for disk drive applications," in Proc. 1992 Int. Symp. Circuits Syst., San Diego, CA, June 1992, pp. 625-628.
4. R. Saban and A. Efendovich A fully-digital, 2-MB/sec, CMOS data separator," in Proc. 1994 Int. Symp. Circuits Syst., vol. 3, London, U.K., June 1994, pp. 53-56.
5. R. E. Best, Phase-Locked Loops: Theory, Design, and Applications. New York: McGraw-Hill, 1984.
6. F. M. Gardner Charge-pump phase-lock loops," IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, Nov. 1980.
7. _ Phase accuracy of charge-pump PUJs," IEEE Trans. Commun., vol. COM-30, pp. 2362-2363, Oct. 1982.
8. H. Meyr and G. Ascheid, Synchronization in Digital Communication: Phase-, Frequency-Locked Loops, and Amplitude Control, vol. 1. New York: Wiley, 1990.
9. M. V. Paemel Analysis of a charge-pump PLL: A new model," IEEE Trans. Commun., vol. 42, pp. 2490-2498, July 1994.
10. T. C. Weigandt, B. Kim, and P. R. Gray Analysis of timing jitter in CMOS ring oscillators," in Proc. 1994 Int. Symp. Circuits Syst., vol. 4, London, U.K., June 1994, pp. 27-30.
11. B. Kim, T. C. Weigandt, and P. R. Gray PLL/DLL system noise analysis for low jitter clock synthesizer design," in Proc. 1994 Int. Symp. Circuits Syst., vol. 4, London, U.K., June 1994, pp. 31-34.
12. J. McNeil Jitter in ring oscillators," in Proc. 1994 Int. Symp. Circuits Syst., vol. 6, London, U.K., June 1994, pp. 201-204.
13. S. K. Enam and A. A. Abidi A 300-MHz CMOS voltage-controlled ring oscillator," IEEE J. Solid-State Circuits, vol. 25, pp. 312-315, Feb. 1990.
14. Y. Savaria, D. Chtchvyrkov, and J. F. Currie A fast CMOS voltage-controlled ring oscillators," in Proc. 1994 Int. Symp. Circuits Syst., London, U.K., vol. 4, June 1994, pp. 359-362.
15. J. McNeil, R. Croughwell, L. D. Vito, and A. Gusinov A 150 mW, 155 MHz phase locked loop with low jitter VCO," in Proc. 1994 Int. Symp. Circuits Syst., vol. 3, London, U.K., June 1994, pp. 49-52.
16. AT&T, Low-Power REACH1 Device, ATT91C010 Advanced Data Sheet, Apr. 1991.
17. K. Ohno and F. Adachi Fast clock synchroniser using initial phase presetting DPLL (IPP-DPLL) for burst signal reception," Electron. Lett., vol. 27, no. 21, pp. 1902-1904, Oct. 1991.
18. M. Banu and A. E. Dunlop Clock recovery circuits with instantaneous locking," Electron. Lett., vol. 28, no. 23, pp. 2127-2129, Nov. 1992.
19. W. D. Llewellyn, M. H. Wong, G. W. Tietz, and P. A. Tucci A 33 Mb/s data synchronizing phase-locked-loop circuit," in 1988 Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1988, pp. 12-13.
20. D. Wulich and M. Bar The convergence of a PLL with variable parameters,"/J./ Circuit Theory Applicat., vol. 18,pp. 135-143, 1990.
21. A. J. Bishop, G. W. Roberts, and M. L. Blostein Adaptive phase locked loop for video signal sampling," in Proc. 1992 Int. Symp. Circuits Syst., San Diego, CA, June 1992, vol. 4, pp. 1664-1667.
22. W. C. Lindsey, Synchronization Systems in Communications and Control. Englewood Cliffs, NJ: Prentice-Hall, 1972.
23. B. Kim High speed clock recovery in VLSI using hybrid analog/digital techniques," Ph.D. dissertation, Univ. California, Berkeley, June 1990.
24. _ Optimal MMSE gear-shifting algorithm for the fast synchronization of DPLL," in Proc. 1993 Int. Symp. Circuits Syst., Chicago, IL, May 1993, vol. 1, pp. 172-175.
25. B. S. Glance New phase-lock loop circuit providing very fast acquisition time," IEEE Trans. Microwave Theory Technol., vol. MTT-23, pp. 747-754, Sept. 1985.
26. H. Sato, K. Kato, T. Sase, I. Ikushima, and S. Kojima A fast pull-in PLL 1C using two-mode pull-in technique," IEICE Trans., vol. J74-B-I, no. 10, pp. 817-824, Oct. 1991.
27. K. M. Ware, H. Lee, and C. G. Sodini A 200-MHz CMOS phase-locked loop with dual phase detectors," IEEE J. Solid-State Circuits, vol. 24, pp. 1560-1568, Dec. 1989.
28. S. Miyazawa, R. Horita, K. Hase, K. Kato, and S. Kojima A BiCMOS PLL-based data separator circuit with high stability and accuracy," IEEE J. Solid-State Circuits, vol. 26, pp. 116-121, Feb. 1991.
29. H. Shirahama, K. Taniguchi, and K. Nakashi A new very fast pull-in PLL system with anti-pseudo-lock function," in Proc. 1993 Symp. VLSI Circuits Dig. Tech. Papers, May 1993, pp. 75-76.
30. Y. Takasaki, Digital Transmission Design and Jitter Analysis. Boston, MA: Artech House, 1991.
31. J. P. Hein and J. W. Scott z-domain model for discrete-time PLL's," IEEE Trans. Circuits Syst., vol. 35, pp. 1393-1400, Nov. 1988.
32. D. H. Wolaver, Phase-Locked Loop Circuit Design,. Englewood Cliffs, NJ: Prentice-Hall, 1991.
33. D.-K Jeong, G. Borriello, D. A. Hodges, and R. H. Katz Design of PLL-based clock generation circuits," IEEE J. Solid-State Circuits, vol. SC-22, pp. 255-261, Apr. 1987.