-
1
-
-
0024918341
-
"A fully depleted lean-channel transistor (DELTA) - A novel vertical ultra thin SOI MOSFET"
-
Dec
-
D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A fully depleted lean-channel transistor (DELTA) - A novel vertical ultra thin SOI MOSFET," in IEDM Tech. Dig., Dec. 1989, pp. 833-836.
-
(1989)
IEDM Tech. Dig.
, pp. 833-836
-
-
Hisamoto, D.1
Kaga, T.2
Kawamoto, Y.3
Takeda, E.4
-
2
-
-
29044440093
-
"FinFET - A self-aligned double-gate MOSFET scalable to 20 nm"
-
Dec
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.-J.8
Bokor, J.9
Hu, C.10
-
3
-
-
0035423513
-
"Pi-gate SOI MOSFET"
-
Aug
-
J. T. Park, J. P. Colinge, and C. H. Diaz, "Pi-gate SOI MOSFET," IEEE Electron Device Lett., vol. 22, no. 8, pp. 405-406, Aug. 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, Issue.8
, pp. 405-406
-
-
Park, J.T.1
Colinge, J.P.2
Diaz, C.H.3
-
4
-
-
4243216494
-
"High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices"
-
Dec
-
J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, "High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices," in IEDM Tech. Dig., Dec. 2001, pp. 19.5.1-19.5.4.
-
(2001)
IEDM Tech. Dig.
-
-
Kedzierski, J.1
Fried, D.M.2
Nowak, E.J.3
Kanarsky, T.4
Rankin, J.H.5
Hanafi, H.6
Natzle, W.7
Boyd, D.8
Zhang, Y.9
Roy, R.A.10
Newbury, J.11
Yu, C.12
Yang, Q.13
Saunders, P.14
Willets, C.P.15
Johnson, A.16
Cole, S.P.17
Young, H.E.18
Carpenter, N.19
Rakowski, D.20
Rainey, B.A.21
Cottrell, P.E.22
Ieong, M.23
Wong, H.-S.P.24
more..
-
5
-
-
33745134066
-
"25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/in the source and drain regions"
-
Jun
-
P. Verheyen, N. Collaert, R. Rooyackers, R. Loo, D. Shamiryan, A. De Keersgieter, G. Eneman, F. Leys, A. Dixit, M. Goodwin, Y. S. Yim, M. Caymax, K. De Meyer, P. Absil, M. Jurczak, and S. Biesemans, "25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/in the source and drain regions," in VLSI Symp. Tech. Dig., Jun. 2005, pp. 194-195.
-
(2005)
VLSI Symp. Tech. Dig.
, pp. 194-195
-
-
Verheyen, P.1
Collaert, N.2
Rooyackers, R.3
Loo, R.4
Shamiryan, D.5
De Keersgieter, A.6
Eneman, G.7
Leys, F.8
Dixit, A.9
Goodwin, M.10
Yim, Y.S.11
Caymax, M.12
De Meyer, K.13
Absil, P.14
Jurczak, M.15
Biesemans, S.16
-
6
-
-
31844435540
-
"Mobility enhancement through substrate engineering"
-
2005-03
-
I. Cayrefourcq, M. Kennard, F. Metral, C. Mazuré, A. Thean, M. Sadaka, T. White, and B. Y. Nguyen, "Mobility enhancement through substrate engineering," in Proc. ECS Silicon-on-Insulator Tech. and Dev. XII, 2005, vol. 2005-03, pp. 191-206.
-
(2005)
Proc. ECS Silicon-on-Insulator Tech. and Dev. XII
, pp. 191-206
-
-
Cayrefourcq, I.1
Kennard, M.2
Metral, F.3
Mazuré, C.4
Thean, A.5
Sadaka, M.6
White, T.7
Nguyen, B.Y.8
-
7
-
-
0036927657
-
"FinFET process refinements for improved mobility and gate work function engineering"
-
Dec
-
Y.-K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Boker, "FinFET process refinements for improved mobility and gate work function engineering," in IEDM Tech. Dig., Dec. 2002, pp. 259-262.
-
(2002)
IEDM Tech. Dig.
, pp. 259-262
-
-
Choi, Y.-K.1
Chang, L.2
Ranade, P.3
Lee, J.-S.4
Ha, D.5
Balasubramanian, S.6
Agarwal, A.7
Ameen, M.8
King, T.-J.9
Boker, J.10
-
8
-
-
0141563604
-
"Band offset induced threshold variation in strained-Si nMOSFETs"
-
Sep
-
J.-S. Goo, Q. Xiang, Y. Takamura, F. Arasnia, E. N. Paton, P. Besser, J. Pan, and M.-R. Lin, "Band offset induced threshold variation in strained-Si nMOSFETs," IEEE Electron Device Lett., vol. 24, no. 9, pp. 568-570, Sep. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.9
, pp. 568-570
-
-
Goo, J.-S.1
Xiang, Q.2
Takamura, Y.3
Arasnia, F.4
Paton, E.N.5
Besser, P.6
Pan, J.7
Lin, M.-R.8
-
9
-
-
20544447617
-
"Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs"
-
Dec
-
S. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs," in IEDM Tech. Dig., Dec. 2004, pp. 221-224.
-
(2004)
IEDM Tech. Dig.
, pp. 221-224
-
-
Thompson, S.1
Sun, G.2
Wu, K.3
Lim, J.4
Nishida, T.5
-
10
-
-
11144354892
-
"A logic nanotechnology featuring strained-silicon"
-
Apr
-
S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," Electron Device Lett., vol. 25, no. 4, pp. 191-193, Apr. 2004.
-
(2004)
Electron Device Lett.
, vol.25
, Issue.4
, pp. 191-193
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Cea, S.4
Chau, R.5
Glass, G.6
Hoffman, T.7
Klaus, J.8
Ma, Z.9
Mcintyre, B.10
Murthy, A.11
Obradovic, B.12
Shifren, L.13
Sivakumar, S.14
Tyagi, S.15
Ghani, T.16
Mistry, K.17
Bohr, M.18
El-Mansy, Y.19
-
11
-
-
21644478626
-
"A systematic study of trade-offs in engineering a locally strained pMOSFET"
-
Dec
-
F. Nouri, P. Verheyen, L. Washington, V. Moroz, I. De Wolf, M. Kawaguchi, S. Biesemans, R. Schreutelkamp, Y. Kim, M. Shen, X. Xu, R. Rooyackers, M. Jurczak, G. Eneman, K. De Meyer, L. Smith, D. Pramanik, H. Forstner, S. Thirupapuliyur, and G. S. Higashi, "A systematic study of trade-offs in engineering a locally strained pMOSFET," in IEDM Tech. Dig., Dec. 2004, pp. 1055-1058.
-
(2004)
IEDM Tech. Dig.
, pp. 1055-1058
-
-
Nouri, F.1
Verheyen, P.2
Washington, L.3
Moroz, V.4
De Wolf, I.5
Kawaguchi, M.6
Biesemans, S.7
Schreutelkamp, R.8
Kim, Y.9
Shen, M.10
Xu, X.11
Rooyackers, R.12
Jurczak, M.13
Eneman, G.14
De Meyer, K.15
Smith, L.16
Pramanik, D.17
Forstner, H.18
Thirupapuliyur, S.19
Higashi, G.S.20
more..
-
12
-
-
33846693940
-
"Piezoresistance effect in germanium and silicon"
-
Apr
-
C. S. Smith, "Piezoresistance effect in germanium and silicon," Phys. Rev., vol. 94, no. 1, pp. 42-49, Apr. 1954.
-
(1954)
Phys. Rev.
, vol.94
, Issue.1
, pp. 42-49
-
-
Smith, C.S.1
-
13
-
-
0000876593
-
"Nonlinear piezoresistance effects in silicon"
-
Feb
-
K. Matsuda, K. Suzuki, K. Yamamura, and Y. Kanda, "Nonlinear piezoresistance effects in silicon," J. Appl. Phys., vol. 73, no. 4, pp. 1838-1847, Feb. 1993.
-
(1993)
J. Appl. Phys.
, vol.73
, Issue.4
, pp. 1838-1847
-
-
Matsuda, K.1
Suzuki, K.2
Yamamura, K.3
Kanda, Y.4
-
14
-
-
26444439083
-
"Exploring the limits of stress-enhanced hole mobility"
-
Sep
-
L. Smith, V. Moroz, G. Eneman, P. Verheyen, F. Nouri, L. Washington, M. Jurczak, O. Penzin, D. Pramanik, and K. De Meyer, "Exploring the limits of stress-enhanced hole mobility," IEEE Electron Device Lett., vol. 26, no. 9, pp. 652-654, Sep. 2005.
-
(2005)
IEEE Electron Device Lett.
, vol.26
, Issue.9
, pp. 652-654
-
-
Smith, L.1
Moroz, V.2
Eneman, G.3
Verheyen, P.4
Nouri, F.5
Washington, L.6
Jurczak, M.7
Penzin, O.8
Pramanik, D.9
De Meyer, K.10
-
15
-
-
13244295296
-
"Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs"
-
Dec
-
T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, T. Maeda, and S. Takagi, "Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs," in IEDM Tech. Dig., Dec. 2003, pp. 33.6.1-33.6.4.
-
(2003)
IEDM Tech. Dig.
-
-
Mizuno, T.1
Sugiyama, N.2
Tezuka, T.3
Moriyama, Y.4
Nakaharai, S.5
Maeda, T.6
Takagi, S.7
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