Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 7, 2006, Pages 1411-1418

  Zhao, Dan ^a   Upadhyaya, Shambhu ^b   Margala, Martin ^c  

^a University of Louisiana at Lafayette   (United States)

^b the State University of New York   (United States)

^c University of Rochester   (United States)

Author keywords

Control routing; Radio frequency (RF) nodes placement; Radio on chip (ROC); System on a chip (SOC) test; Wireless test control architectures

Indexed keywords

FREQUENCIES; INTEGRATED CIRCUITS; LOCAL AREA NETWORKS; OPTIMIZATION; PROBLEM SOLVING; RADIO SYSTEMS; WIRELESS TELECOMMUNICATION SYSTEMS;

CONTROL ROUTING; RADIO FREQUENCY (RF) NODES PLACEMENT; RADIO-ON-CHIP (ROC); SYSTEM-ON-A-CHIP (SOC) TEST; WIRELESS TEST CONTROL ARCHITECTURES;

MICROPROCESSOR CHIPS;

EID: 33744811155     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.855919     Document Type: Article

References (28)

1. K. Chakrabarty, "Test scheduling for cote-based systems using mixed-integer linear programming," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 10, pp. 1163-1174, Oct. 2000.
2. _, "Design of system-on-a-chip test access architectures using integer linear programming," in Proc. IEEE VLSI Test Symp., Montreal, QC, Canada, 2000, pp. 127-134.
3. M. F. Chang, V. P. Roychowdhury, L. Zhang, H. Shin, and Y. Qian, "RF/wireless interconnect for inter- and intra-chip communications," Proc. IEEE, vol. 89, no. 4, pp. 456-466, Apr. 2001.
4. V. Chv'atal, "A greedy heuristic for the set-covering problem," Math. Oper. Res., vol. 4, no. 3, pp. 233-235, Aug. 1979.
5. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2nd ed. Cambridge, MA: MIT Press, 2001.
6. G. L. Craig, C. R. Kime, and K. K. Saluja, "Test scheduling and control for VLSI built-in self-test," IEEE Trans. Comput., vol. 37, no. 9, pp. 1099-1109, Sep. 1988.
7. H. Eberle, A. Wander, and N. Gura, "Testing systems wirelessly," in Proc. IEEE VLSI Text Symp., Napa Valley, CA, Apr. 2004, pp. 335-340.
8. B. A. Floyd, "A CMOS wireless interconnect system for Multigigahertz clock distribution," Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. Florida, Gainesville, 2001.
9. B. A. Floyd, C. Hung, and K. K. O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 543-552, May 2002.
10. M. Franceschetti, M. Cook, and J. Bruck, "A geometric theorem for approximate disk covering algorithms," Caltech Univ., Pasadena, CA, Paradise Tech. Rep. ETR035, Jan. 2001.
11. _, "A geometric theorem for wireless network design optimization," presented at the Lee Center Advanced Network Workshop, Pasadena, CA, Oct. 2002, unpublished.
12. P. Guerrier and A. Greiner, "A scalable architecture for system-on-chip interconnections," in Proc. Sophia Antipolis Forum MicroElectronics, Sophia Antipolis, France, Oct. 1999, pp. 90-93.
13. S. Hochbaum and W. Maass, "Approximation schemes for covering and packing problems in image processing and VLSI," J. ACM, vol. 32, no. 1, pp. 130-136, Jan. 1985.
14. Y. Huang et al., "Resource allocation and test scheduling for concurrent test of core-based SoC design," in Proc. IEEE Asian Test Symp., Kyoto, Japan, Nov. 2001, pp. 265-270.
15. International Technology Roadmap for Semiconductors, (2003). 1TRS 2003 Edition. [Online]. Available: http://public.itrs.net/Files/ 2003ITRS/Home2003. htm.
16. V. Iyengar, K. Chakrabarty, and E. J. Marinissen, "Test wrapper and test access mechanism co-optimization for system-on-a-chip," in Proc. IEEE Int. Test Conf., Baltimore, MD, 2001, pp. 1023-1032.
17. K. Lahiri, G. Lakshminarayana, A. Raghunathan, and S. Dey, "Communications architecture tuners: A methodology for the design of high-performance communication architectures for system-on-chip," in Proc. IEEE/ACM Design Automation Conf., Los Angeles, CA, Jun. 2000, pp. 513-518.
18. E. Larsson and Z. Peng, "Test scheduling and scan-chain division under power constraint," in Proc. IEEE Asian Test Symp., Kyoto, Japan, Nov. 2001, pp. 259-264.
19. K. Lee and C. Huang, "A hierarchical test control architecture for core based design," in Proc. IEEE Asian Test Symp., Taipei, Taiwan, R.O.C., Dec. 2000, pp. 248-253.
20. J. Li et al., "A hierarchical test scheme for system-on-chip designs," in Proc. Design, Automation and Test Europe Conf., Paris, France, Mar. 2002, pp. 486-490.
21. S. Misra, S. Subramanian, and P. P. Chaudhuri, "A control constrained test scheduling approach for VLSI circuits," in Proc. IEEE Asian Text Symp., Hiroshima, Japan, Nov. 1992, pp. 145-150.
22. B. Moore, C. Backhouse, and M. Margala, "Design of wireless submicron characterization system," in Proc. IEEE VLSI Test Symp., Napa Valley, CA, Apr. 2004, pp. 341-346.
23. F. DaSilva, Y. Zorian, L. Whetsel, K. Arabi, and R. Kapur, "Overview of the IEEE P1500 Standard," in Proc. IEEE Int. Teat Conf., Charlotte, NC, Oct. 2003, pp. 988-997.
24. A. S. Tanenbaum, Computer Networks. Upper Saddle River, NJ: Prentice-Hall, 1996.
25. D. Wingard, "MicroNetwork-based integration for SOCs," in Proc. IEEE Design Automation Conf., Las Vegas, NV, Jun. 2001, pp. 673-677.
26. D. Zhao and S. Upadhyaya, "Adaptive test scheduling in SoCs by dynamic partitioning," in Proc. IEEE Int. Symp. Defect and Fault Tolerance VLSI Systems, Vancouver, BC, Canada, Nov. 2002, pp. 334-342.
27. _, "Power constrained test scheduling with dynamically varied TAM," in Proc. IEEE VLSI Test Symp., Napa Valley, CA, May 2003, pp. 273-278.
28. Y. Zorian, "A distributed BIST control scheme for complex VLSI devices," in Proc. IEEE VLSI Text Symp., Atlantic City, NJ, Apr. 1993, pp. 4-9.