A PAB-based multi-prefetcher mechanism

International Journal of Parallel Programming

Volumn 34, Issue 2, 2006, Pages 171-188

  Gendler, Alexander ^a,b   Mendelson, Avi ^b   Birk, Yitzhak ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^b INTEL CORPORATION   (Israel)

Author keywords

Cache tag pressure; Memory wall; Prefetching

Indexed keywords

ARRAYS; BUFFER STORAGE; COMPUTER APPLICATIONS;

CACHE TAG PRESSURE; MEMORY WALL; PREFETCHING;

DATA STORAGE EQUIPMENT;

EID: 33744799987     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10766-006-0006-1     Document Type: Article

References (25)

1. A. J. Smith, Cache Memories, Computing Surveys, 14(3):473-530 (Sep. 1982).
2. T. F. Chen and J. L. Baer, An Effective On-chip Preloading Scheme to Reduce Data Access Penalty, Proceedings of Supercomputing 91, pp. 176-186 (Nov. 1991).
3. Intel Co.: Intel Pentium 4 and Intel Xeon Processor Optimization, http://cache-www. intel.com/cd/00/00/01/76/17672.24896607.pdf or developer.intel.com.
4. Apple Computer, Inc., Technical note TN2087: PowerPC G5 Performance Primer, http://developer, apple.com/technotes/tn/tn2087.html.
5. S. P. Vanderwiel and D. J. Lijia, Data Prefetch Mechanisms, ACM Computing Surveys, 32(2): 174-199 (Jun. 2000).
6. J. Tse and A. J. Smith, CPU Cache Prefetching: Timing Evaluation of Hardware Implementations, IEEE Transactions on Computers, 47(5):509-526 (May 1998).
7. C. J. Hughes and S. V. Adve, Memory-Side Prefetching for Linked Data Structures, Technical Report UIUCDCS-R-2001-2221, Univ. or Illinois UC (May 2001).
8. M. Karlson, F. Magnus, and P. Stenstrom, A Prefetching Technique for Irregular Accesses to Linked Data Structures, Proceedings of the 6th International Symposium on High-Performance Computer Architecture (HPCA), pp. 206-217 (Jan. 2000).
9. N. Kohout, S. Choi, D. Kim, and D. Yeung, Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism For Pointer-Chasing Codes, Proceedings of yhe International Conference on Parallel Architectures and Compilation Techniques, pp. 268-279 (Sep. 2001).
10. J. C. Chiu, S. A. Chi, and C. P. Chung, Instruction Cache Prefetching Directed by Branch Prediction, IEE Proceedings - Computers & Digital Techniques, 146(5):241-246 (Sep. 1999).
11. C-K. Luk and T.C. Mowry, Architectural and Compiler Support for Effective Instruction Prefetching: A Cooperative Approach, ACM Transactions on Computer Systm, 19(1):71-109 (Feb. 2001).
12. G. S. Manku, M. R. Prasad, and D. A Patterson, A New Voting Based Hardware Data Prefetch Scheme, Proceedings of the 4th International Conference on High Performance Computing, pp. 100-105 (Dec. 1997).
13. T. L. Johnson, D. A. Connors, and W-M.W. Hwu, Run-time Adaptive Cache management, Proceedings of the 31st Hawaii International Conference on System Sciences, vol. 7, pp. 774-775 (1998).
14. A. Ki and A. E. Knowles, Adaptive Data Prefetching Using Cache Information, Proceedings 11th International Conference on Supercomputing, pp. 204-212 (1997).
15. R. Pendse and H. Katta, Selective Prefetching: Prefetching when Only Required, Proceedings of the 42nd Midwest Symposium on Circuits and Systems, vol. 2, pp. 866-869 (Aug. 1999).
16. P. Reungsang, S. K. Park, G. Lee, S. -W. Jeong, and H. -L. Roh, Reducing Cache Pollution of Prefetching in a Small Data Cache, Procedings of the International Conference on Computer Design (ICCD), pp. 530-533 (Sep. 2001).
17. IBM, POWER-3: Next generation 64-bit PowerPC Processor Design, www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power3wp.html.
18. A. Cristal, O. J. Santana, M. Valero, and J. F. Martinez, Toward Kilo-Instruction Processors, ACM Transactions Architect and Code Opt., 1: 289-417 (2004).
19. J. W. Fu, J. H. Patel, and B. L. Jansen, Stride Directed Prefetching in Scalar Processors, Proceedings of the International Symposium on Microarchitecture (MICRO-25), pp. 102-110 (Dec. 1992).
20. I. Sklenar, Prefetch Unit for Vector Operation on Scalar Computers, Proceedings 19th International Symposium on Computer Architecture (ISCA), pp. 31-37 (May 1992).
21. H. Yu and G. Kedem, DRAM-page Based Data Prediction and Prefetching, Proceedings International Conference on Computer Design (ICCD), pp. 267-275 (Sep. 2000).
22. T. F. Chen and J. L. Baer, Effective Hardware-Based Data Prefetching for High Performance Processors, IEEE Transaction on Computers. 44(5): 609-623 (May 1995).
23. J. F. Cantin and M. D. Hill, Cache Performance for SPEC CPU2000 Benchmarks, http://www.cs.wisc.edu/multifacet/misc/spec2000cache-data/.
24. T. Austin, E. Larson, and D. Ernst, SimpleScalar: An Infrastructure for Computer System Modeling, IEEE Computer, 35(2): 59-67 (Feb. 2002).
25. A. Gendler, Efficient Multi-Prefetcher Architectures using a Prefetcher Assessment Buffer (PAB), MSc Dissertation, Electrical Eng. Dept., Technion (2005).