Novel high-density low-power high-performance double-gate logic techniques

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 122-123

  Chiang, Meng Hsueh ^a   Kim, Keunwoo ^b   Tretz, Christophe ^c   Chuang, Ching Te ^b  

^a NATIONAL ILAN UNIVERSITY   (Taiwan)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); NAND CIRCUITS; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; THIN FILMS; THRESHOLD VOLTAGE;

DOUBLE-GATE LOGIC TECHNIQUES; JUNCTION CAPACITANCE; LOGIC BASED APPROACH; LOGIC FUNCTIONS;

LOGIC GATES;

EID: 16244391429     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. E. J. Nowak et al., IEEE Circuits & Devices Mag., p. 20, Jan/Feb 2004.
2. Y. X. Liu et al., Tech. Dig. IEDM, p. 986, 2003.
3. S. Mitra et al., Proc. IEEE Int. SOI Conf., p. 66,2002.
4. S. Mitra et al., Proc. IEEE Int. SOI Conf., p. 177, 2003.
5. Taurus-MEDICI, Synopsis, Inc., 2003.