Synchronization processor synthesis for latency insensitive systems

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 896-897

  Bomel, Pierre ^a   Martin, Eric ^a   Boutillon, Emmanuel ^a  

^a UNIVERSITÉ DE BRETAGNE SUD   (France)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; OPTIMIZATION; SYNCHRONIZATION;

LATENCY INSENSITIVE SYSTEMS (LIS); LOCAL IP PERFORMANCES; SYNCHRONIZATION PROCESSOR;

PROGRAM PROCESSORS;

EID: 33646945900     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.287     Document Type: Conference Paper

References (6)

1. L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, "Theory of Latency-Insensitive Design," in. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 20(9) :18, Sept. 2001
2. International Technology Roadmap for Semiconductors, 2003 edition.
3. L. P. Carloni and A.L. Sangiovanni-Vincentelli, "Coping with Latency in SoC Design," in IEEE Micro, Special Issue on Systems on Chip, 22(5) :12, Oct. 2002.
4. M. Singh and M. Theobald, "Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures," in Proceedings of the Design Automation and Test in Europe Conference (DATE'04), Paris, Feb. 2004.
5. M. R. Casu and L. Macchiarulo, "A New Approach to Latency Insensitive Design," in Proceedings, of the Design and Automation Conference (DAC'04), San Diego, June 2004.
6. GAUT, web site, http://web.univ-ubs.fr/gaut