Cycle accurate binary translation for simulation acceleration in rapid prototyping of SoCs

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 792-797

  Schnerr, Jürgen ^a   Bringmann, Oliver ^a   Rosenstiel, Wolfgang ^a,b  

^a FZI RESEARCH CENTER FOR INFORMATION TECHNOLOGY   (Germany)

^b UNIVERSITY OF TÜBINGEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; INTERFACES (COMPUTER); PARALLEL PROCESSING SYSTEMS; TRANSLATION (LANGUAGES);

BINARY TRANSLATOR; PARALLEL CYCLE GENERATION; TRIGGERS CYCLE; VLIW PROCESSOR;

RAPID PROTOTYPING;

EID: 33646906207     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.106     Document Type: Conference Paper

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