Optimized cell structure for FinFET array flash memory

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 289-292

  Cho, E S ^a   Kim, T Y ^a   Lee, C H ^a   Lee, C ^a   Yoon, J M ^a   Cho, H J ^a   Kang, H S ^a   Ahn, Y J ^a   Park, Donggun ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; DIELECTRIC MATERIALS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; OPTIMIZATION; SILICON WAFERS; TRANSISTORS;

CELL ARRAYS; COUPLING RATIO; DEVICE FABRICATION; FLASH AREA;

FLASH MEMORY;

EID: 17644402133     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. Y. Kim, et al., VLSI2003, p11
2. B. Doyle, et al, VLSI 2003, p133.
3. T. Misuno, IEEE ELECTRON DEVICE LETTERS, VOL.24, NO.4, APRIL. 2003.
4. C.H.Lee, et al VLSI2004 to be presented