-
1
-
-
0003783814
-
-
3rd ed. Norwall, MA: Kluwer
-
J. P. Colinge, SOI Technology, Materials to VLSI, 3rd ed. Norwall, MA: Kluwer, 2004, pp. 229-231.
-
(2004)
SOI Technology, Materials to VLSI
, pp. 229-231
-
-
Colinge, J.P.1
-
2
-
-
0037646045
-
"Advanced depleted-substrate transistors: Single-gate, double-gate and tri-gate"
-
Nagoya, Japan
-
R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Dockzy, R. Arghavani, and S. Datta, "Advanced depleted-substrate transistors: Single-gate, double-gate and tri-gate," in Proc. SSDM, Nagoya, Japan, 2002, pp. 68-69.
-
(2002)
Proc. SSDM
, pp. 68-69
-
-
Chau, R.1
Doyle, B.2
Kavalieros, J.3
Barlage, D.4
Murthy, A.5
Dockzy, M.6
Arghavani, R.7
Datta, S.8
-
3
-
-
0035423513
-
"Pi-gate SOI MOSFET"
-
May
-
J.-T. Park, J.-P. Colinge, and C. H. Diaz, "Pi-gate SOI MOSFET," IEEE Electron Device Lett., vol. 22, pp. 405-406, May 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, pp. 405-406
-
-
Park, J.-T.1
Colinge, J.-P.2
Diaz, C.H.3
-
4
-
-
0036932378
-
"25 nm CMOS omega FETs"
-
F.-L. Yang, H.-Y. Chen, F.-C. Cheng, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang, and C. Hu, "25 nm CMOS omega FETs," in IEDM Tech. Dig., 2002, pp. 255-258.
-
(2002)
IEDM Tech. Dig.
, pp. 255-258
-
-
Yang, F.-L.1
Chen, H.-Y.2
Cheng, F.-C.3
Huang, C.-C.4
Chang, C.-Y.5
Chiu, H.-K.6
Lee, C.-C.7
Chen, C.-C.8
Huang, H.-T.9
Chen, C.-J.10
Tao, H.-J.11
Yeo, Y.-C.12
Liang, M.-S.13
Hu, C.14
-
5
-
-
10844227309
-
"Substrate effects in SOI FinFETs"
-
J. Pretet, F. Daugé, A. Vandoóren, L. Mathew, B. Y. Nguyen, J. Jomaah, and S. Cristoloveanu, "Substrate effects in SOI FinFETs," in Proc. Electrochem. Soc., vol. 2003-05, 2003, pp. 231-236.
-
(2003)
Proc. Electrochem. Soc.
, vol.5
, pp. 231-236
-
-
Pretet, J.1
Daugé, F.2
Vandoóren, A.3
Mathew, L.4
Nguyen, B.Y.5
Jomaah, J.6
Cristoloveanu, S.7
-
6
-
-
0442311975
-
"Coupling effects and channels separation in FinFETs"
-
F. Daugé, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B. Y. Nguyen, "Coupling effects and channels separation in FinFETs," Solid State Electron., vol. 48, pp. 535-542, 2004.
-
(2004)
Solid State Electron.
, vol.48
, pp. 535-542
-
-
Daugé, F.1
Pretet, J.2
Cristoloveanu, S.3
Vandooren, A.4
Mathew, L.5
Jomaah, J.6
Nguyen, B.Y.7
-
7
-
-
10844223592
-
-
Femlab Simulator. Comsol, Inc. [Online]. Available
-
Femlab Simulator. Comsol, Inc. [Online]. Available: http://www.comsol.com/
-
-
-
-
8
-
-
0023422261
-
"Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs"
-
H.-S. Wong, M. H. White, T. J. Krutsck, and R. V. Booth, "Modeling of transconductance degradation and threshold voltage in thin oxide MOSFETs," Solid State Electron., vol. 30, no. 9, pp. 953-968, 1987.
-
(1987)
Solid State Electron.
, vol.30
, Issue.9
, pp. 953-968
-
-
Wong, H.-S.1
White, M.H.2
Krutsck, T.J.3
Booth, R.V.4
-
9
-
-
0028427763
-
"Modeling of ultrathin double-gate nMOS.SOI transistors"
-
P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, "Modeling of ultrathin double-gate nMOS.SOI transistors," Solid State Electron. vol. 41, no. 5, pp. 715-720, 1994.
-
(1994)
Solid State Electron.
, vol.41
, Issue.5
, pp. 715-720
-
-
Francis, P.1
Terao, A.2
Flandre, D.3
Van de Wiele, F.4
-
10
-
-
0036999661
-
"Multiple-gate SOI MOSFETS: Device design guidelines"
-
Dec
-
J. T. Park and J. P. Colinge, "Multiple-gate SOI MOSFETS: Device design guidelines," IEEE Trans. Electron Devices, vol. 49, pp. 2222-2229, Dec. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 2222-2229
-
-
Park, J.T.1
Colinge, J.P.2
-
11
-
-
1442360362
-
"Multiple-gate SOI MOSFETs"
-
J. P. Colinge, "Multiple-gate SOI MOSFETs," Solid State Electron. vol. 48/6, pp. 897-905, 2004.
-
(2004)
Solid State Electron.
, vol.48
, Issue.6
, pp. 897-905
-
-
Colinge, J.P.1
-
12
-
-
10844269580
-
"SOI for hostile environment applications"
-
J. P. Colinge, "SOI for hostile environment applications," in Proc. Int. SOI Conf., 2004, pp. 1-4.
-
(2004)
Proc. Int. SOI Conf.
, pp. 1-4
-
-
Colinge, J.P.1
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