A reversible version of 4 × 4 bit array multiplier with minimum gates and garbage outputs

Proceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05

Volumn , Issue , 2005, Pages 106-113

  Thapliyal, Himanshu ^a   Srinivas, M B ^a   Arabnia, Hamid R ^b  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b Large Scale Distributed Information Systems   (United States)

Author keywords

Reversible logic; Reversible multiplier

Indexed keywords

FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS; LOGIC GATES;

ARRAY MULTIPLIERS; BINARY ARRAYS; BINARY NUMBERS; DESIGN TECHNIQUES; GARBAGE OUTPUTS; NOVEL DESIGNS; NUMBER OF GATES; REVERSIBLE CIRCUITS; REVERSIBLE LOGIC; REVERSIBLE MULTIPLIER;

EMBEDDED SYSTEMS;

EID: 33646515665     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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