메뉴 건너뛰기




Volumn 3312, Issue , 2004, Pages 98-112

Combining equivalence verification and completion functions

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; RECONFIGURABLE HARDWARE;

EID: 35048841157     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30494-4_8     Document Type: Article
Times cited : (5)

References (6)
  • 1
    • 0036500942 scopus 로고    scopus 로고
    • Verification of out-of-order processor designs using model checking
    • March
    • S. Berezin, E. M. Clarke, A. Biere, and Y. Zhu. Verification of out-of-order processor designs using model checking. Formal Methods in System Design, 20(2):159-186, March 2002.
    • (2002) Formal Methods in System Design , vol.20 , Issue.2 , pp. 159-186
    • Berezin, S.1    Clarke, E.M.2    Biere, A.3    Zhu, Y.4
  • 2
    • 84958772916 scopus 로고
    • Automatic verification of pipelined microprocessor control
    • Springer Verlag, July
    • J. R. Burch and D. L. Dill. Automatic verification of pipelined microprocessor control. In CAV, pages 68-70. Springer Verlag, July 1994.
    • (1994) CAV , pp. 68-70
    • Burch, J.R.1    Dill, D.L.2
  • 6
    • 84893735603 scopus 로고    scopus 로고
    • Using rewriting rules and positive equality to formally verify wide-issue out-of-order microprocessors with a reorder buffer
    • Mar.
    • M. Velev. Using rewriting rules and positive equality to formally verify wide-issue out-of-order microprocessors with a reorder buffer. In DATE, pages 28-35, Mar. 2002.
    • (2002) DATE , pp. 28-35
    • Velev, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.