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Volumn , Issue , 2005, Pages 4839-4842

A flexible ADC approach for mixed-signal SoC platforms

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN COMPLEXITY; DIGITAL SYSTEM; MIXED SIGNAL; OVERALL DESIGN; PIPELINED ARCHITECTURE; PLATFORM BASED DESIGN; PROGRAMMABILITY; SOC PLATFORMS; SYSTEMS-ON-CHIP; TIME-TO-MARKET;

EID: 33645975994     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465716     Document Type: Conference Paper
Times cited : (12)

References (13)
  • 1
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    • T. A. C. M. Claassen, .Platform design: The next paradigm shift to deal with complexity,. in International Symposium on VLSI Technology, Systems and Applications, 2003, Oct. 6 . 8 2003, pp. 8.12.
    • T. A. C. M. Claassen, .Platform design: The next paradigm shift to deal with complexity,. in International Symposium on VLSI Technology, Systems and Applications, 2003, Oct. 6 . 8 2003, pp. 8.12.
  • 4
    • 0038575223 scopus 로고    scopus 로고
    • D. Buss et al., .SoC CMOS technology for Personal Internet Products,. IEEE Trans. Electron Devices, 50, no. 3, pp. 546.556, Mar. 2003.
    • D. Buss et al., .SoC CMOS technology for Personal Internet Products,. IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 546.556, Mar. 2003.
  • 5
    • 0026390411 scopus 로고    scopus 로고
    • E. K. F. Lee and P. G. Gulak, .A CMOS Field-Programmable Analog Array,. IEEE J. Solid-State Circuits, 26, no. 12, pp. 1860.1867, Dec. 1991.
    • E. K. F. Lee and P. G. Gulak, .A CMOS Field-Programmable Analog Array,. IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1860.1867, Dec. 1991.
  • 6
    • 27644531835 scopus 로고    scopus 로고
    • S. Mortezapour and E. K. F. Lee, .Recon-gurable Analog Integrated Circuit Architecture based on Switched-Capacitor Techniques,. in Proc. IEEE ISCAS 2001, 4, 2001, pp. 314.317.
    • S. Mortezapour and E. K. F. Lee, .Recon-gurable Analog Integrated Circuit Architecture based on Switched-Capacitor Techniques,. in Proc. IEEE ISCAS 2001, vol. 4, 2001, pp. 314.317.
  • 7
    • 67649091527 scopus 로고    scopus 로고
    • P. Setty, J. Barner, J. Plany, H. Burger, and J. Sonntag, .A 5.75b 350MS/s or 6.75b 150MS/s Recon-gurable Flash ADC for a PRML Read Channel,. in Proc. IEEE ISSCC 1998, 1, 1998, pp. 148.149, 428.
    • P. Setty, J. Barner, J. Plany, H. Burger, and J. Sonntag, .A 5.75b 350MS/s or 6.75b 150MS/s Recon-gurable Flash ADC for a PRML Read Channel,. in Proc. IEEE ISSCC 1998, vol. 1, 1998, pp. 148.149, 428.
  • 8
    • 0035690894 scopus 로고    scopus 로고
    • K. Gulati and H.-S. Lee, .A Low-Power Recon-gurable ADC,. IEEE J. Solid-State Circuits, 36, no. 12, pp. 1900.1911, Dec. 2001.
    • K. Gulati and H.-S. Lee, .A Low-Power Recon-gurable ADC,. IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1900.1911, Dec. 2001.
  • 9
    • 0026836960 scopus 로고    scopus 로고
    • S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, .A 10-b 20-MSample/s Analog-to-Digital Converter,. IEEE J. Solid-State Circuits, 27, no. 3, pp. 351.358, Mar. 1992.
    • S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, .A 10-b 20-MSample/s Analog-to-Digital Converter,. IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351.358, Mar. 1992.
  • 10
    • 0027853599 scopus 로고    scopus 로고
    • A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, .A 15-b 1-MSample/s Digitally Self-Calibrated Pipeline ADC,. IEEE J. Solid-State Circuits, 28, no. 12, pp. 1207.1215, Dec. 1993.
    • A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, .A 15-b 1-MSample/s Digitally Self-Calibrated Pipeline ADC,. IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207.1215, Dec. 1993.
  • 11
    • 0348233280 scopus 로고    scopus 로고
    • B. Murmann and B. E. Boser, .A 12-bit 75-MS/s Pipelined ADC using Open-Loop Residue Ampli-cation,. IEEE J. Solid-State Circuits, 38, no. 12, pp. 2040.2050, Dec. 2003.
    • B. Murmann and B. E. Boser, .A 12-bit 75-MS/s Pipelined ADC using Open-Loop Residue Ampli-cation,. IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040.2050, Dec. 2003.
  • 12
    • 0037630792 scopus 로고    scopus 로고
    • K. Poulton et al., .A 20 GS/s 8-b ADC with a 1 MB memory in 0.18-m CMOS,. in Proc. IEEE ISSCC 2003, 1, 2003, pp. 318.496.
    • K. Poulton et al., .A 20 GS/s 8-b ADC with a 1 MB memory in 0.18-m CMOS,. in Proc. IEEE ISSCC 2003, vol. 1, 2003, pp. 318.496.
  • 13
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    • P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, .A ratio-independent algorithmic analog-to-digital conversion technique,. IEEE J. Solid-State Circuits, 19, no. 6, pp. 828.836, Dec. 1984.
    • P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, .A ratio-independent algorithmic analog-to-digital conversion technique,. IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 828.836, Dec. 1984.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.