A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2001, Pages 419-424

  Chung, Steve S ^a   Chen, S J ^a   Yang, W J ^a   Yang, J J ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b CHANG GUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRON TRAPS; GATES (TRANSISTOR); HOT CARRIERS; RELIABILITY; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE;

CHANNEL SHORTENING INDUCED OXIDE DAMAGE; DRAIN CURRENT; SHALLOW-TRENCH-ISOLATION;

MOSFET DEVICES;

EID: 0034995006     PISSN: 00999512     EISSN: None     Source Type: Journal    
DOI: 10.1109/RELPHY.2001.922936     Document Type: Article

References (7)

1. Anomalous hot-carrier induced degradation in very narrow channel nMOSFET's with STI structure
2. Degradation of hot carrier lifetime for narrow width MOSFET with shallow trench isolation
3. Enhanced hot-carrier induced degradation in shallow trench isolation narrow channel PMOSFET's
4. Positive oxide-charge generation during 0.25um PMOSFET hot-carrier degradation
5. Examination of gradual-junction p-MOS structure for hot carrier control using a new lifetime extraction method
6. Anomalous hot-carrier behavior for LDD p-channel transistors
7. Analysis of hot-carrier-induced degradation mode on pMOSFET's