Enhanced copper ECP for 45 nm devices

Semiconductor International

Volumn 28, Issue 11, 2005, Pages 55-61

  Hafezi, Hooman ^a   Huang, Yi Chiau ^a,b   Zhang, Amy ^a,c   Singh, Saravjeet ^a   Ngai, Chris ^a,d  

^a APPLIED MATERIALS INC   (United States)

^b Applied Materials ^*

^c SlimCell Technology

^d Maydan Technology Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUXILIARY CATHODE; CMP DEFECTS; HIGH-PRECISION WAFER-IMMERSION SEQUENCE;

CATHODES; DEFECTS; ELECTRIC FIELD EFFECTS; ELECTROPLATING; SILICON WAFERS;

COPPER PLATING;

EID: 33645654519     PISSN: 01633767     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (5)

1. S. Parikh et al., "300 mm Copper Low-k Integration and Reliability for 90 and 65 nm Nodes," IITC Proceedings, 2004, p. 60.
2. J. Flake, J.P. Jacqueman, M. Hartig, E. Sicurani and P. Vannier, "Transient Behavior in Copper Electrofilling," Abstract 944, 206th Meet. of the Electrochemical Soc., 2004.
3. T. Park, et al. "Chip-Scale Modeling of Electro plated Copper Surface Profiles," J. Electrochem. Soc., 2004, Vol. 151, No. 6, p. C418.
4. K. Smekalin, R. Cheung and D. Tribula, "Tuning the Process Flow to Optimize Copper CMP," Solid State Technology, September 2001.
5. H. Hafezi, A. Rosenfeld, S. Singh, J. Dukovic and M. Birang, "Copper Electrodeposition on Thin-Seed Substrates," 207th Meet, of the Electrochemical Soc., May 2005.