Tuning the process flow to optimize copper CMP

Solid State Technology

Volumn 44, Issue 9, 2001, Pages 107-108+110+112

  Smekalin, K ^a   Cheung, R ^a   Tribula, D ^a  

^a APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DIELECTRIC MATERIALS; MICROPROCESSOR CHIPS; PERFORMANCE; SEMICONDUCTOR DEVICE MANUFACTURE;

COPPER DUAL DAMASCENE; ELECTROCHEMICAL PLATING; INTERLAYER DIELECTRIC DEPOSITION;

CHEMICAL MECHANICAL POLISHING;

EID: 0035448511     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (8)

1. Cooper CMP and effect of dummy structures
2. Yield implications of wafer edge engineering
3. Impact of low-temperature anneals of electroplated copper films on copper CMP removal rates
4. Copper CMP and process control
5. Corrosion control during Cu CMP
6. Copper CMP defect reduction using POU filtration
7. Extraction of planarization length and response function in chemical-mechanical polishing