Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

Superconductor Science and Technology

Volumn 19, Issue 5, 2006, Pages

  Nagasawa, Shuichi ^a   Hinode, Kenji ^a   Satoh, Tetsuro ^a   Kitagawa, Yoshihiro ^a   Hidaka, Mutsuo ^a  

^a SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; ELECTRIC CLOCKS; ELECTRIC LINES; ENERGY DISSIPATION; QUANTUM THEORY; SENSORS;

MEMORY CELL ARRAYS; PIPELINE STRUCTURE; SINGLE FLUX QUANTUM (SFQ) CIRCUITS; SUPERCONDUCTING LOOP DRIVER;

RANDOM ACCESS STORAGE;

EID: 33645550520     PISSN: 09532048     EISSN: 13616668     Source Type: Journal    
DOI: 10.1088/0953-2048/19/5/S34     Document Type: Article

References (4)

1. Nagasawa S, Hasegawa H, Hashimoto T, Suzuki H, Miyahara K and Enomoto Y 1999 Design of a 16 kbit superconducting latching/SFQ hybrid RAM Supercond. Sci. Technol. 12 933-6
2. Nagasawa S, Hasegawa H, Hashimoto T, Suzuki H, Miyahara K and Enomoto Y 2001 Superconducting latching/SFQ hybrid RAM IEEE Trans. Appl. Supercond. 11 533-6
3. Nagasawa S, Hinode K, Satoh T, Akaike H, Kitagawa Y and Hidaka M 2004 Development of advanced Nb process for SFQ circuits Physica C 412-414 1429-36
4. Faris S M, Henkels W H, Valsamakis E A and Zappe H H 1980 Basic design of a Josephson technology cache memory IBM J. Res. Dev. 24 143-54