Superconducting latching/SFQ hybrid RAM

IEEE Transactions on Applied Superconductivity

Volumn 11, Issue 1 I, 2001, Pages 533-536

  Nagasawa, S ^a   Hasegawa, H ^a   Hashimoto, T ^a   Suzuki, H ^a   Miyahara, K ^a   Enomoto, Y ^a  

^a SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

Josephson junction; Latching device; Random access memory; Single flux quantum device

Indexed keywords

BUFFER CIRCUITS; ELECTRIC INVERTERS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; LOGIC GATES; RANDOM ACCESS STORAGE; SQUIDS;

ADDRESS BUFFER; LATCHING SENSE CIRCUITS; SINGLE FLUX QUANTUM DEVICE; SUPERCONDUCTING LATCHING DEVICES; VORTEX TRANSITIONAL MEMORY CELLS;

JOSEPHSON JUNCTION DEVICES;

EID: 0035267924     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/77.919400     Document Type: Conference Paper

References (8)

1. Design of a 16Kbit superconducting latching/SFQ hybrid RAM
2. A single flux quantum cryogenic random access memory
3. Towards a 16 kilobit, sub-nanosecond Josephson RAM
4. A 2-kbit superconducting memory chip
5. Superconducting SFQ-NOR decoder
6. A 380ps, 9.5mW Josephson 4-Kbit RAM operated at a high bit yield
7. High-frequency clock operation of Josephson 256-word × 16-bit RAMs
8. New RSFQ circuits