Design of a 16 kbit superconducting latching/SFQ hybrid RAM

Superconductor Science and Technology

Volumn 12, Issue 11, 1999, Pages 933-936

  Nagasawa, Shuichi ^a   Hasegawa, Haruhiro ^a   Hashimoto, Tatsunori ^a   Suzuki, Hideo ^a   Miyahara, Kazunori ^a   Enomoto, Youichi ^a  

^a SUPERCONDUCTIVITY RESEARCH LABORATORY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CRITICAL CURRENTS; EQUIVALENT CIRCUITS; FLIP FLOP CIRCUITS; HYBRID COMPUTERS; IMPEDANCE MATCHING (ELECTRIC); LOGIC GATES;

BLOCK DECODERS; IMPEDANCE MATCHED LINES; LATCHING BLOCK DRIVERS; LATCHING BLOCK SENSES; MATRIX ARRAYS; SINGLE FLUX QUANTUM;

RANDOM ACCESS STORAGE;

EID: 0033226232     PISSN: 09532048     EISSN: None     Source Type: Journal    
DOI: 10.1088/0953-2048/12/11/371     Document Type: Article

References (4)

1. Nagasawa S, Hashimoto Y, Numata H and Tahara S 1995 A 380 ps, 9.5 mW Josephson 4-Kbit RAM operated at a high bit yield IEEE Trans. Appl. Supercond. 5 2447-52
2. Nagasawa S, Numata H, Hashimoto Y and Tahara S 1997 High-frequency clock operation of Josephson memories ISEC'97 Extended Abstracts D31, pp 290-2
3. Nagasawa S, Numata H, Hashimoto Y and Tahara S 1999 High-frequency clock operation of Josephson 256-word × 16-bit RAMs IEEE Trans. Appl. Supercond. at press
4. Polonsky S, Semenov V K, Bunyk P I, Kirichenko A F, Kidiyarova-Shevchenko A Yu, Mukhanov O A, Shevchenko P N, Schneider D F, Zinoviev D Yu and Likharev K K 1993 New RSFQ circuits IEEE Trans. Appl. Supercond. 3 2566-77