High speed signal sampler by multiple-path algorithm

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn A, Issue , 2004, Pages

  Tsai, Guo Ruey ^a   Lin, Min Chuan ^a  

^a KUN SHAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; BANDWIDTH; COMPARATOR CIRCUITS; DATA STORAGE EQUIPMENT; ELECTRIC CONVERTERS; ELECTRICAL ENGINEERING; REAL TIME SYSTEMS; SAMPLING;

AID CONVERTERS; DATA MEMORIES; MULTIPLE-PATH ALGORITHMS; PERIODIC SIGNALS;

SIGNAL PROCESSING;

EID: 27944439751     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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5. Takamoto Watanabe, Shigenori Yamauchi "An All-Digital PLL for Frequency Multiplication by 4 to 1022 with Seven-Cycle Lock Time", IEEE J. solid-state circuits, Vol.38, No.2, pp. 198-204, Feb., 2003.