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Volumn , Issue , 2000, Pages 235-240
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Register allocation for common subexpressions in DSP data paths
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Author keywords
[No Author keywords available]
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Indexed keywords
CODE OPTIMIZATION TECHNIQUE;
DSP APPLICATION;
DSP PROCESSOR;
IRREGULAR DATA;
MEMORY ACCESS;
REGISTER ALLOCATION;
SIMULATED ANNEALING ALGORITHMS;
SUB-EXPRESSIONS;
DATA FLOW ANALYSIS;
DATA FLOW GRAPHS;
OPTIMIZATION;
COMPUTER AIDED DESIGN;
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EID: 33644678286
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/368434.368618 Document Type: Conference Paper |
Times cited : (9)
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References (16)
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