-
4
-
-
0033358971
-
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
-
August
-
K. Ghose and M. B. Kamble. Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers and Bit-Line Segmentation. Proc. Int'l Symp. on Low Power Electronics and Design, pp. 70-75, August 1999.
-
(1999)
Proc. Int'l Symp. on Low Power Electronics and Design
, pp. 70-75
-
-
Ghose, K.1
Kamble, M.B.2
-
5
-
-
84962779213
-
MiBench: A free, commercially representative embedded benchmark suite
-
December
-
th Workshop on Workload Characterization, pp. 3-14, December 2001.
-
(2001)
th Workshop on Workload Characterization
, pp. 3-14
-
-
Guthaus, M.R.1
Ringenberg, J.2
Ernst, D.3
Austin, T.4
Mudge, T.5
Brown, R.6
-
8
-
-
1642310480
-
Circuit and microarchitectural techniques for reducing cache leakage power
-
February
-
N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge. Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power. IEEE Transactions on VLSI, Vol. 12, No. 2, pp. 167-184, February 2004.
-
(2004)
IEEE Transactions on VLSI
, vol.12
, Issue.2
, pp. 167-184
-
-
Kim, N.S.1
Flautner, K.2
Blaauw, D.3
Mudge, T.4
-
9
-
-
0033889397
-
Filtering memory references to increase energy efficiency
-
January
-
J. Kin, M. Gupta, and W. H. Mangione-Smith. Filtering Memory References to Increase Energy Efficiency. IEEE Transactions on Computers, Vol. 49, No. 1, pp. 1-15, January 2000.
-
(2000)
IEEE Transactions on Computers
, vol.49
, Issue.1
, pp. 1-15
-
-
Kin, J.1
Gupta, M.2
Mangione-Smith, W.H.3
-
12
-
-
0030673565
-
A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor
-
January
-
J. Montanaro, et al. A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. Digital Technical Journal, Vol. 9 No. 1, pp. 49-62, January 1997.
-
(1997)
Digital Technical Journal
, vol.9
, Issue.1
, pp. 49-62
-
-
Montanaro, J.1
-
13
-
-
0242555935
-
Comparison of state-preserving vs. non-state-preserving leakage control in caches
-
June
-
nd Annual Workshop on Duplicating, Deconstructing, and Debunking, pp. 14-24, June 2003.
-
(2003)
nd Annual Workshop on Duplicating, Deconstructing, and Debunking
, pp. 14-24
-
-
Parikh, D.1
Zhang, Y.2
Sankaranarayanan, K.3
Skadron, K.4
Stan, M.5
-
14
-
-
0033672408
-
Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories
-
July 2000
-
M. Powell, S-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. Proc. Int'l Symp. on Low Power Electronics and Design, 2000, pp. 90-95, July 2000.
-
(2000)
Proc. Int'l Symp. on Low Power Electronics and Design
, pp. 90-95
-
-
Powell, M.1
Yang, S.-H.2
Falsafi, B.3
Roy, K.4
Vijaykumar, T.N.5
-
16
-
-
34249306904
-
HotLeakage: A temperature-aware model of subthreshold and gate leakage for architects
-
University of Virginia Department of Computer Science, March
-
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical Report CS-2003-05, University of Virginia Department of Computer Science, March 2003.
-
(2003)
Technical Report
, vol.CS-2003-05
-
-
Zhang, Y.1
Parikh, D.2
Sankaranarayanan, K.3
Skadron, K.4
Stan, M.5
-
17
-
-
0035177403
-
Adaptive mode-control: A static-power-efficient cache design
-
September
-
H. Zhou, M. Toburen, E. Rotenberg, and T. Conte. Adaptive mode-control: A Static-Power-Efficient Cache Design. Proc. Int'l Conf. on Parallel Arch, and Compilation Techniques, pp. 61-70, September 2001.
-
(2001)
Proc. Int'l Conf. on Parallel Arch, and Compilation Techniques
, pp. 61-70
-
-
Zhou, H.1
Toburen, M.2
Rotenberg, E.3
Conte, T.4
|