Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO2 universal mobility with an EOT= ∼1 nm

IEEE Electron Device Letters

Volumn 27, Issue 3, 2006, Pages 185-187

  Zhang, Zhibo ^a   Song, S C ^b   Quevedo Lopez, M A ^a   Choi, Kisik ^b   Kirsch, Paul ^c   Lysaght, Pat ^b   Lee, Byoung Hun ^c  

^a TEXAS INSTRUMENTS   (United States)

^b SEMATECH   (United States)

^c IBM   (United States)

Author keywords

Charge carrier mobility; HfO2; HfSiON; High gate dielectric; Metal gate; MOSFETs

Indexed keywords

CARRIER MOBILITY; DIELECTRIC MATERIALS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; OPTIMIZATION; PHASE TRANSITIONS; SILICA; TITANIUM COMPOUNDS;

CHARGE CARRIER MOBILITY; EQUIVALENT OXIDE THICKNESS (EOT); GATE DIELECTRICS; METAL GATE;

MOSFET DEVICES;

EID: 33644630331     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.870245     Document Type: Article

References (11)

1. H. R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G. A. Brown, C. D. Young, P. M. Zeitzoff, J. Gutt, P. Lysaght, M. I. Gardner, and R. W. Murto, "High-k gate stacks for planar, scaled CMOS integrated circuits," Microelectron. Eng., vol. 69, no. 2-4, pp. 152-167, 2003.
2. T. P. Ma, "High-k gate dielectrics for scaled CMOS technology," in Proc. ICSSICT, 2001, pp. 297-302.
3. 2 gate stacks," IEDM Tech. Dig., pp. 825-828, 2004.
4. W. J. Zhu, J.-P. Han, and T. P. Ma, "Mobility measurement and degradation mechanisms of MOSFET's made with ultra thin high-κ dielectrics," IEEE Trans. Electron Devices, vol. 51, no. 1, pp. 98-105, Jan. 2004.
5. 2/TaN low thermal-budget n-channel FET's with solid-phase epitaxially regrown (SPER) junctions," VLSI Symp. Tech. Dig., pp. 234-235, 2005.
6. P. D. Kirsch, J. H. Sim, S. C. Song, S. Krishnan, J. Peterson, H.-J. Li, M. Quevedo-Lopez, C. D. Young, R. Choi, N. Moumen, P. Majhi, Q. Wang, J. G. Ekerdt, G. Bersuker, and B. H. Lee, "Mobility enhancement of high-κ gate stacks through reduced transient charging," in Proc. EESDERC, 2005, pp. 367-370.
7. M. A. Quevedo-Lopez, S. A. Krishnan, P. D. Kirsch, H. J. Li, J. J. Peterson, and B. H. Lee, "Enhanced mobility and reliability in ultrascaled HfSiON gate dielectrics through suppressed crystallization," Appl. Phys. Lett., submitted for publication.
8. 2 MISFET with sub-1 nm EOT," VLSI Symp. Tech. Dig., pp. 228-229, 2005.
9. J. Widiez, M. Vinet, T. Poiroux, P. Hollinger, B. Previtali, P. Grosgeorges, M. Mouis, and S. Deleonibus, "TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties," in Proc. IEEE Int. SOI Conf., 2005, pp. 30-31.
10. 2/TiN gate stack," IEDM Tech. Dig., pp. 653-656, 2003.
11. C. D. Young, P. Zeitzoff, G. A. Brown, G. Bersuker, B. H. Lee, and J. R. Hauser, "Intrinsic mobility evaluation of high-κ gate dielectric transistors using pulsed Id-Vg," IEEE Electron Device Lett., vol. 16, no. 8, pp. 586-589, Aug. 2005.