Validating word-oriented processors for bit and multi-word operations

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3189, Issue , 2004, Pages 473-488

  Lee, Ruby B ^a   Yang, Xiao ^a   Shi, Zhijie Jerry ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; DIGITAL SIGNAL PROCESSING; GENERAL PURPOSE COMPUTERS; MOBILE SECURITY; NETWORK SECURITY;

BIT-LEVEL OPERATIONS; COMPUTING PARADIGM; CRYPTOGRAPHY ALGORITHMS; GENERAL PURPOSE PROCESSORS; INSTRUCTION SET ARCHITECTURE; MICRO ARCHITECTURES; PROCESSOR ARCHITECTURES; SECURITY FUNCTIONS;

COMPUTER ARCHITECTURE;

EID: 35048849907     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30102-8_40     Document Type: Article

References (20)

1. B. Schneier, Applied Cryptography, 2nd Ed., John Wiley & Sons, Inc., 1996.
2. NIST (National Institute of Standards and Technology), "Advanced Encryption Standard (AES) - FIPS Pub. 197", November 2001.
3. J. Burke, J. McDonald and T. Austin, "Architectural support for fast symmetric-key cryptography", Proceedings of ASPLOS 2000, pp. 178-189. November 2000.
4. L. Wu, C. Weaver, and T. Austin, "CryptoManiac: a fast flexible architecture for secure communication", Proceedings of the 28th International Symposium on Computer Architecture, pp. 110-119, June 2001.
5. R. B. Lee, Z. Shi, and X. Yang, "Efficient permutation instructions for fast software cryptography", IEEE Micro, vol. 21, no. 6, pp. 56-69, December 2001.
6. R. B. Lee, "Subword parallelism with MAX-2", IEEE Micro, Vol. 16, No. 4, pp. 51-59, August 1996.
7. K. Diefendorff et al, "AltiVec extension to PowerPC accelerates media processing", IEEE Micro, Vol. 20, No. 2, pp. 85-95, March/April 2000.
8. "IA-64 application developer's architecture guide", Intel Corp., May 1999.
9. X. Yang, M. Vachharajani, and R. B. Lee, "Fast subword permutation instructions based on butterfly networks", Proceedings of SPIE 2000, pp. 80-86, January 2000.
10. X. Yang and R. B. Lee, "Fast subword permutation instructions using omega and flip network stages", Proceedings of the International Conference on Computer Design, pp. 15-22, September 2000.
11. Z. Shi and R. B. Lee, "Bit permutation instructions for accelerating software cryptography", Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 138-148, July 2000.
12. J. P. McGregor and R. B. Lee, "Architectural enhancements for fast subword permutations with repetitions in cryptographic applications", Proceedings of the International Conference on Computer Design, pp. 453-461, September 2001.
13. R. B. Lee, Z. Shi, and X. Yang, "How a processor can permute n bits in O(1) cycles", Proceedings of Hot Chips 14 - A Symposium on High Performance Chips, August 2002.
14. S. Palacharla, N. P. Jouppi, and J. E. Smith, "Complexity-effective superscalar processors", Proceedings of the 24th Annual International Symposium on Computer Architecture, pp. 206-218, 1997.
15. J. A. Farell and T. C. Fischer, "Issue logic for a 600-mhz out-of-order execution microprocessor", IEEE Journal of Solid-State Circuits, Vol. 33, Issue 5, pp. 707-712, May 1998.
16. S. Onder and R. Gupta, "Superscalar execution with direct data forwarding", Proceedings of the 1998 ACM/IEEE Conference on Parallel Architectures and Compilation Techniques, pp. 130-135, 1998.
17. D. S. Henry, B. C. Kuszmaul, G. H. Loh, and R. Sami, "Circuits for wide-window superscalar processors", Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 236-247, 2000.
18. R. Canal, A. Gonzalez, "A Low-complexity issue logic", Proceedings of the 14th international conference on Supercomputing, pp. 327-335, 2000
19. J. Stark, M. D. Brown, and Y. N. Patt, "On pipelining dynamic instruction scheduling logic", Proceedings of the 33th Annual ACM/IEEE International Symposium on Microarchitecture, pp. 57-66, 2000.
20. M. D. Brown, J. Stark, and Y. N. Patt, "Select-free instruction scheduling logic", Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture, pp. 204-213, December 2001.