FE-I2: A front-end readout chip designed in a commercial 0.25-μm process for the ATLAS pixel detector at LHC

IEEE Transactions on Nuclear Science

Volumn 51, Issue 4 I, 2004, Pages 1358-1364

  Blanquart, L ^a   Richardson, J ^a   Einsweiler, K ^a   Fischer, P ^b   Mandelli, E ^a   Meddeler, G ^a   Peric, I ^c  

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^b UNIVERSITY OF MANNHEIM   (Germany)

^c UNIVERSITY OF BONN   (Germany)

Author keywords

Active bias distribution; Hybrid pixel sensor; Leakage current compensation; Multlchip module; Shielding technique; Threshold adjustment; Time over threshold

Indexed keywords

ACTIVE BIAS DISTRIBUTION; HYBRID PIXEL SENSOR LEAKAGE CURRENT COMPENSATION; MULTICHIP MODULE; SHEILDING TECHNIQUE; THRESHOLD ADJUSTMENT; TIME OVER THRESHOLD;

CALIBRATION; CAPACITANCE; COMPUTER SIMULATION; COUPLINGS; DATA RECORDING; ELECTROMAGNETIC DISPERSION; GRAPH THEORY; MATHEMATICAL MODELS; PARTICLE ACCELERATORS; RADIATION; SIGNAL PROCESSING; VOLTAGE MEASUREMENT;

PARTICLE DETECTORS;

EID: 3342915500     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.832895     Document Type: Conference Paper

References (7)

1. G. Anelli et al., "Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: Practical design aspects," IEEE Trans. Nucl. Sci., vol. 46, pp. 1690-1696, Dec. 1999.
2. J. Richardson, "The ATLAS pixel front-end readout chips," Nucl. Instrum. Methods A, vol. 473, pp. 157-162, 2001.
3. L. Blanquart et al., "Analog front-end cell designed in a commercial 0.25 μm process for the ATLAS pixel detector at LHC," IEEE Trans. Nucl. Sci., vol. 49, pp. 1778-1782, Aug. 2002.
4. L. Blanquart, A. Mekkaoui, V. Bonzom, and P. Delpierre, "Pixel analog cell prototypes for ATLAS in DMILL technology," Nucl. Instrum. Methods A, vol. 395, no. 3, pp. 313-317, 1997.
5. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2874-2878, Dec. 1996.
6. E. Mandelli et al., "Digital column readout architecture for the ATLAS pixel 0.25 μm front end IC," IEEE Trans. Nucl. Sci., vol. 49, pp. 1774-1777, Aug. 2002.
7. J. C. Chen, D. Sylvester, and C. Hu, "An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution," IEEE Trans. Semiconduct. Manufact., vol. 11, pp. 204-210, May 1998.