A failure analysis test structure for deep sub-micron CMOS copper interconnect technologies

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2005, Pages 245-249

  Cabrini, A ^a   Cantarelli, D ^b   Cappelletti, P ^b   Casiraghi, R ^b   Iezzi, D ^b   Maurelli, A ^b   Pasotti, M ^b   Rolandi, P L ^b   Torelli, G ^a  

^a UNIVERSITY OF PAVIA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGRADATION; STATISTICAL METHODS;

CMOS TECHNOLOGY; INTEGRATION PROCESSES; TEST STRUCTURES;

MICROELECTRONICS;

EID: 27644597381     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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