Hardness-by-design approach for 0.15 μm fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

IEEE Transactions on Nuclear Science

Volumn 52, Issue 6, 2005, Pages 2524-2530

  Makihara, A ^a   Midorikawa, M ^a   Yamaguchi, T ^a   Iide, Y ^a   Yokose, T ^a   Tsuchiya, Y ^a   Arimitsu, T ^a   Asai, H ^b   Shindou, H ^b   Kuboyama, S ^b   Matsuda, S ^b  

^a High Reliability Engineering and Components Corporation   (Japan)

^b JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

Author keywords

Commercial process; Fully depleted complementary metal oxide semiconductor silicon on insulator (CMOS SOI); Hardness by design (HBD); Single event transient (SET); Single event upset (SEU)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; FLIP FLOP CIRCUITS; RADIATION HARDENING; SILICON ON INSULATOR TECHNOLOGY;

COMMERCIAL PROCESS; HARDNESS-BY-DESIGN (HBD); SINGLE-EVENT TRANSIENT (SET); SINGLE-EVENT UPSET (SEU);

LOGIC DEVICES;

EID: 33144473428     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.860716     Document Type: Conference Paper

References (7)

1. V. Ferlet-Cavrois, G. Vizkelethy, P. Paillet, A. Torres, J. R. Schwank, M. R. Shaneyfelt, J. Baggio, J. du Port de Pontcharra, and L. Tosti, "Charge enhancement effect in NMOS bulk transistors induced by heavy ion irradiation - Comparison with SOI," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3255-3262, Dec. 2004.
2. P. E. Dodd, M. R. Shaneyfelt, D. S. Walsh, J. R. Schwank, G. L. Hash, R. A. Loemker, B. L. Draper, and P. S. Winokur, "Single-event upset and snapback in silicon-on-insulator devices and integrated circuits," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2165-2174, Dec. 2000.
3. O. Musseau, V. Ferlet-Cavrois, J. L. Pelloie, S. Buchner, D. McMorrow, and A. B. Campbell, "Laser probing of bipolar amplification in 0.25-μm MOS/SOI transistors," IEEE Trans. Nucl. Sci., no. 6, pp. 2196-2203, Dec. 2000. Col. 47.
4. J. R. Schwank, V. Ferlet-Cavrois, M. R. Shaneyfelt, P. Paillet, and P. E. Dodd, "Radiation effects in soi technologies," IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 522-538, Jun. 2003.
5. P. E. Dodd, M. R. Shaneyfelt, K. M. Horn, D. S. Walsh, T. A. Hill, B. L. Draper, J. R. Schwank, F. W. Sexton, and P. S. Winokur, "SEU-sensitive volumes in bulk and SOI SRAM's from first-principles calculations and experiments," IEEE Trans. Nucl. Sci., vol. 48, no. 6, pp. 1893-1903, Dec. 2001.
6. P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, and T. Turflinger, "Single event transient pulsewidth measurements using a variable temporal latch technique," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3365-3368, Dec. 2004.
7. A. Makihara, T. Yamaguchi, Y. Tsuchiya, T. Arimitsu, H. Asai, Y. Iide, H. Shindou, S. Kuboyama, and S. Matsuda, "SEE in a 0.15 μm fully depleted CMOS/SOI commercial process," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3621-3625, Dec. 2004.