On measurement of effective silicon backend strength using bump pull/shear techniques

Proceedings of the ASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems: Advances in Electronic Packaging 2005

Volumn PART B, Issue , 2005, Pages 965-969

  Sane, Sandeep ^a   Chandran, Biju ^a   Tandon, Shalabh ^a   Sorenson, Leanord R ^a   Alazar, Tsgereda ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY DISPERSIVE SPECTROSCOPY; OPTICAL INTERCONNECTS; RELIABILITY; SCANNING ELECTRON MICROSCOPY; SOLDERING ALLOYS; STIFFNESS; STRENGTH OF MATERIALS;

ASSEMBLY FLUX; HIGHLY ACCELERATED STEAM TEST (HAST); SHEAR METROLOGIES;

SILICON;

EID: 32844462031     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/ipack2005-73306     Document Type: Conference Paper

References (6)

1. Chandran, B, et. al., "The Mechanical Side of Ultra-Low K: Can it Take the Strain?", Future Fab Intl., Volume 17.
2. Frutschy, Kris J, et al., "Rapid Die Heating for Low Stress Die Attach", IEEE Transactions on Device and Materials Reliability, Volume 4, #2, June 2004.
3. Kloster,G., et,. al., "Porosity effects on low-k dielctric film strength and interfacial adhesion", Interconnect Technology Conference, June 5 2002.
4. Scherban, T., et. al., Interfacial adhesion of copper-low k interconnects, 2001 IEEE interconnect technology conference, pp 257-259.
5. Jang et.al., 2000 ECTC, pp 64-68
6. Shinji Baba, et. al, "Flip chip BGA Applied High Density Organic Substrate", ECTC, 1999.