An optimal adder-based hardware architecture for the DCT/SA-DCT

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5960, Issue 3, 2005, Pages 1410-1417

  Kinane, Andrew ^a   Muresan, Valentin ^a   O'Connor, Noel ^a  

^a DUBLIN CITY UNIVERSITY   (Ireland)

Author keywords

ACE Profile; DCT; Hardware Acceleration; Low Power; MPEG 4; Object Coding; SA DCT; VLSI

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COSINE TRANSFORMS; SIGNAL PROCESSING; VLSI CIRCUITS;

ACE PROFILE; DCT; HARDWARE ACCELERATION; LOW POWER; MPEG-4; OBJECT CODING; SA-DCT;

COMPUTER HARDWARE;

EID: 32544446537     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.633190     Document Type: Conference Paper

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