-
1
-
-
0034497409
-
Low-complexity fusion of intensity, motion, texture and edge for image sequence segmentation: A neural network approach
-
Sydney, Australia, Dec.
-
J. Kim and T. Chen, "Low-complexity fusion of intensity, motion, texture and edge for image sequence segmentation: A neural network approach," in IEEE Int. Workshop Neural Networks for Signal Processing, Sydney, Australia, Dec. 2000, pp. 497-606.
-
(2000)
IEEE Int. Workshop Neural Networks for Signal Processing
, pp. 497-606
-
-
Kim, J.1
Chen, T.2
-
2
-
-
0004124275
-
-
MPEG Requirement Group, MPEG-4 Overview, 2001.
-
(2001)
MPEG-4 Overview
-
-
-
6
-
-
0013360546
-
-
TMS320C6000 [Online]
-
TMS320C6000 [Online]. Available: http://www.ti.com/does/products/dsp/index.htm.
-
-
-
-
7
-
-
0013361354
-
-
ADSP-2100 Family [Online]
-
ADSP-2100 Family [Online]. Available: http://www.analog.com/industry/dsp/overview/general.html#adsp.
-
-
-
-
8
-
-
0029777661
-
An architectural overview of the programmable multimedia processor, TM-1
-
S. Rathnam and G. Slavenburg, "An architectural overview of the programmable multimedia processor, TM-1," in Proc. COMPCON, 1996, pp. 319-326.
-
(1996)
Proc. COMPCON
, pp. 319-326
-
-
Rathnam, S.1
Slavenburg, G.2
-
9
-
-
0031363925
-
A media processor for multimedia signal processing applications
-
E. Holmann, T. Yoshida, and A. Mohri, "A media processor for multimedia signal processing applications," in IEEE Workshop Signal Processing Systems, 1997, pp. 86-96.
-
(1997)
IEEE Workshop Signal Processing Systems
, pp. 86-96
-
-
Holmann, E.1
Yoshida, T.2
Mohri, A.3
-
10
-
-
0032203856
-
VLSI implementations of image and video multimedia processing systems
-
Nov.
-
P. Pirsch and H.-J. Stolberg, "VLSI implementations of image and video multimedia processing systems," IEEE Trans. Circuits Syst. Video Technol., vol. 8, pp. 878-891, Nov. 1998.
-
(1998)
IEEE Trans. Circuits Syst. Video Technol.
, vol.8
, pp. 878-891
-
-
Pirsch, P.1
Stolberg, H.-J.2
-
11
-
-
0032203807
-
"Fractal engine: An affine video processor core for multimedia applications
-
Nov.
-
O. Gatemi and S. Panchanathan, "Fractal engine: An affine video processor core for multimedia applications," IEEE Trans. Circuits Syst. Video Technol., vol. 8, pp. 892-908, Nov. 1998.
-
(1998)
IEEE Trans. Circuits Syst. Video Technol.
, vol.8
, pp. 892-908
-
-
Gatemi, O.1
Panchanathan, S.2
-
12
-
-
0013362129
-
A VLSI architecture for dynamic scene analysis
-
Mar.
-
N. Ranganathan and R. Mehrotra, "A VLSI architecture for dynamic scene analysis," Comput. Vis., Graph., and Image Processing: Image Understanding, pp. 189-197, Mar. 1991.
-
(1991)
Comput. Vis., Graph., and Image Processing: Image Understanding
, pp. 189-197
-
-
Ranganathan, N.1
Mehrotra, R.2
-
13
-
-
0033284733
-
A pipelined architecture for image segmentation by adaptive progressive thresholding
-
K. V. Asari, T. Srikanthan, S. Kumar, and D. Radhakrishnan, "A pipelined architecture for image segmentation by adaptive progressive thresholding," Microprocessors and Microsyst., vol. 23, pp. 493-498, 1999.
-
(1999)
Microprocessors and Microsyst.
, vol.23
, pp. 493-498
-
-
Asari, K.V.1
Srikanthan, T.2
Kumar, S.3
Radhakrishnan, D.4
-
14
-
-
0027666921
-
Design and implementation of a low-level image segmentation architecture-LISA
-
W. F. Blanz, C. B. Shung, C. E. Cox, W. Greiner, B. E. Dom, and D. Petkovic, "Design and implementation of a low-level image segmentation architecture-LISA," Machine Vis. Applic., vol. 6, pp. 181-190, 1993.
-
(1993)
Machine Vis. Applic.
, vol.6
, pp. 181-190
-
-
Blanz, W.F.1
Shung, C.B.2
Cox, C.E.3
Greiner, W.4
Dom, B.E.5
Petkovic, D.6
-
15
-
-
0035452223
-
Multiple feature clustering for image sequence segmentation
-
Sept.
-
J. Kim and T. Chen, "Multiple feature clustering for image sequence segmentation," Pattern Recognit. Lett., vol. 22, pp. 1207-1217, Sept. 2001.
-
(2001)
Pattern Recognit. Lett.
, vol.22
, pp. 1207-1217
-
-
Kim, J.1
Chen, T.2
-
17
-
-
0025489075
-
The self-organizing map
-
Sept.
-
T. Kohonen, "The self-organizing map," Proc. IEEE, vol. 78, pp. 1464-1480, Sept. 1990.
-
(1990)
Proc. IEEE
, vol.78
, pp. 1464-1480
-
-
Kohonen, T.1
-
18
-
-
0031247746
-
A real time edge detector: Algorithm and VLSI architecture
-
F. Alzahrani and T. Chen, "A real time edge detector: Algorithm and VLSI architecture," Real-Time Imaging, vol. 3, pp. 363-378, 1997.
-
(1997)
Real-Time Imaging
, vol.3
, pp. 363-378
-
-
Alzahrani, F.1
Chen, T.2
-
19
-
-
0032804087
-
A VLSI architecture for real-time edge linking
-
Amjad and T. Chen, "A VLSI architecture for real-time edge linking," IEEE Trans. Pattern Anal. Machine Intell., vol. 21, pp. 89-94, 1999.
-
(1999)
IEEE Trans. Pattern Anal. Machine Intell.
, vol.21
, pp. 89-94
-
-
Amjad1
Chen, T.2
-
20
-
-
0019923189
-
Why systolic architecture?
-
Jan.
-
H. T. Kung, "Why systolic architecture?," IEEE Comput., pp. 37-46, Jan. 1982.
-
(1982)
IEEE Comput.
, pp. 37-46
-
-
Kung, H.T.1
-
21
-
-
0030085283
-
VLSI architectures for block matching algorithms using systolic arrays
-
Feb.
-
S. B. Pan, S. S. Chae, and R. H. Park, "VLSI architectures for block matching algorithms using systolic arrays," IEEE Trans. Circuits Syst. Video Technol., vol. 6, pp. 67-73, Feb. 1996.
-
(1996)
IEEE Trans. Circuits Syst. Video Technol.
, vol.6
, pp. 67-73
-
-
Pan, S.B.1
Chae, S.S.2
Park, R.H.3
-
22
-
-
0025415006
-
Design and implementation of a ganeral-purpose median filter unit in CMOS VLSI
-
Apr.
-
M. Karaman, L. Onural, and A. Atalar, "Design and implementation of a ganeral-purpose median filter unit in CMOS VLSI," IEEE J. Solid-State Circuits, vol. 25, pp. 505-513, Apr. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 505-513
-
-
Karaman, M.1
Onural, L.2
Atalar, A.3
-
23
-
-
0025508206
-
Optimal size integer division circuits
-
Oct.
-
J.H. Reif and S. R. Tate, "Optimal size integer division circuits," SIAM J. Comput., pp. 912-924, Oct. 1990.
-
(1990)
SIAM J. Comput.
, pp. 912-924
-
-
Reif, J.H.1
Tate, S.R.2
-
24
-
-
0027149754
-
Design and FPGA implementation of efficient integer arithmetic algorithms
-
A. Saha and R. Krishnamurthy, "Design and FPGA implementation of efficient integer arithmetic algorithms," in Proc. Southeast Conf. 1993.
-
(1993)
Proc. Southeast Conf.
-
-
Saha, A.1
Krishnamurthy, R.2
-
25
-
-
84958059004
-
Exponential lower bounds on the size of OBDD's representing integer division
-
T. Horiyama and S. Yajima, "Exponential lower bounds on the size of OBDD's representing integer division," in Proc. ISAAC'97, 1997, pp. 163-172.
-
(1997)
Proc. ISAAC'97
, pp. 163-172
-
-
Horiyama, T.1
Yajima, S.2
-
27
-
-
0020886345
-
The VLSI complexity of sorting
-
C. D. Thompson, "The VLSI complexity of sorting," IEEE Trans. Comput., vol. C-32, pp. 1171-1184, 1983.
-
(1983)
IEEE Trans. Comput.
, vol.C-32
, pp. 1171-1184
-
-
Thompson, C.D.1
-
28
-
-
0033712949
-
A VLSI architecture for image sequence segmentation using edge fusion
-
Padova, Italy, Sept.
-
J. Kim and T. Chen, "A VLSI architecture for image sequence segmentation using edge fusion," in Int. Workshop on Computer Architectures for Machine Perception, Padova, Italy, Sept. 2000, pp. 57-66.
-
(2000)
Int. Workshop on Computer Architectures for Machine Perception
, pp. 57-66
-
-
Kim, J.1
Chen, T.2
|