Energy-efficient hardware architecture for variable N-point ID DCT

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3254, Issue , 2004, Pages 780-788

  Kinane, Andrew ^a   Muresan, Valentin ^a   O'Connor, Noel ^a   Murphy, Noel ^a   Marlow, Sean ^a  

^a DUBLIN CITY UNIVERSITY   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

COSINE TRANSFORMS; DISCRETE COSINE TRANSFORMS; HARDWARE; IMAGE CODING; MOTION PICTURE EXPERTS GROUP STANDARDS; RECONFIGURABLE HARDWARE;

BATTERY POWERED; DISCRETE COSINE TRANSFORM(DCT); DISTRIBUTED ARITHMETIC; ENERGY EFFICIENT; HARDWARE ACCELERATION; HARDWARE ARCHITECTURE; MPEG-4 VIDEO CODEC; WIRELESS PLATFORM;

ENERGY EFFICIENCY;

EID: 35048885695     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30205-6_80     Document Type: Article

References (11)

1. Sikora, T., Makai B., Shape-Adaptive DCT for Generic Coding of Video, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 5, No. 1, February 1995, pp 59-62.
2. Muresan, V., Kinane, A., Larkin, D., Hardware Acceleration Architectures for MPEG-based Mobile Video Platforms: A Brief Overview, Proc. 4th European Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), London, April 2003, pp 456-461.
3. Butts, J.A., et al. A Static Power Model for Architects, 33rd International Symposium on Microarchitecture, December 2000.
4. Ruby, W., (Low) Power To The People, EDAVision Magazine, March 2002.
5. Poppen, F., Low Power Design Guide, Low Power Design and Services Group, OFFIS Research Institute, http://wwiv.lowpower.de [Accessed 16th Sep. 2003].
6. MPEG-4: Information Technology - Coding of Audio Visual Objects - Part 2: Visual, ISO/IEC 14496-2, Amendment 1, July 15th 2000.
7. Xanthopoulos, T., Chandrakasan, A.P., A Low-Power DCT Core Using Adaptive Bitwidth and Arithmetic Activity Exploiting Signal Correlations and Quantization, IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, May 2000, pp 740 - 750.
8. Shams, A., Pan, W., Chidanandan, A., Bayouni, M.A., A Low Power High Performance Distributed DCT Architecture, Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2002 (ISVLSI'02).
9. Potkonjak, M., Srivastava, M.B., Chandrakasan, A.P., Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 2, February 1996, pp 151 - 165.
10. Kinane, A., Power-Efficient Hardware Accelerator for MPEG-4 Shape Adaptive Discrete Cosine Transform Tool Software Demo, Internal Technical Report, Visual Media Processing Group, DCU, February 2004.
11. Mattavelli, M., Turney, R., Text of ISO/IEC DTR 14496-9 Information technology - Coding of audio visual objects - Part 9: Reference hardware description, ISO/IEC 14496-9, Pattaya, March 2003.