Logic design for printability using OPC methods

IEEE Design and Test of Computers

Volumn 23, Issue 1, 2006, Pages 30-37

  Lucas, Kevin ^a   Yuan, Chi Min ^a   Boone, Robert ^a   Wimmer, Karl ^a   Strozewski, Kirk ^a   Toublan, Olivier ^b  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LITHOGRAPHY; LOGIC CIRCUITS; OPTIMIZATION; PRODUCT DESIGN;

LITHOGRAPHIC PATTERN CONTROL; POST TAPEOUT OPTIMIZATION; PRINTABILITY; PRODUCT DESIGN ANALYSIS;

LOGIC DESIGN;

EID: 32144446417     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2006.18     Document Type: Article

References (6)

1. International Technology Roadmap for Semiconductors, Semiconductor Industry Assoc., 1994.
2. R. Radojcic and M. Rencher, "Old Rules No Longer Apply," EE Times, Nov. 2005; http://img.cmpnet.com/eedesign/2003/ inside_eedesign5.pdf.
3. K. Lucas et al., "Combining OPC and Design for Printability into 65 nm Logic Designs," Proc. SPIE, vol. 5379-21, 2004, pp. 158-169.
4. C. Krautshik et al., "Impact of EUV Light Scatter on CD Control as a Result of Mask Density Changes," Proc. SPIE, vol. 4688, 2002, pp. 289-301.
5. J. Cobb et al., "Flare Compensation in EUV Lithography," 2003; http://www.sematech.org/resources/litho/meetings/euvl/20030930/ presentations/5D%20Cobb%20EUV%20Symp.pdf.
6. H. Chuang et al., "Practical Applications of 2-D Optical Proximity Corrections for Enhanced Performance of 0.25 um Random Logic Devices," Technical Digest Int'l Electron Devices Meeting, IEEE Press, 1997, pp. 483-486.