"Sea of Kelvin" multiple-pattern arrangement interconnect characterization for Low-k/Cu dual damascene and its findings

Proceedings of the IEEE 2004 International Interconnect Technology Conference

Volumn , Issue , 2004, Pages 211-213

  Okazaki, M ^a   Hatano, M ^a   Yoshida, K ^a   Shibasaki, S ^a   Kaneko, H ^a   Yoda, T ^a   Hayasaka, N ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESION; COPPER; DIELECTRIC MATERIALS; PHYSICAL VAPOR DEPOSITION; SHRINKAGE; STRESS ANALYSIS; TRANSMISSION ELECTRON MICROSCOPY; VLSI CIRCUITS;

DAMASCENE STRUCTURE; INTERCONNECT PATTERN DESIGN; RESISTANCE SHIFT;

INTERCONNECTION NETWORKS;

EID: 3142691353     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. E. T. Ogawa, et al., "Stress-induced voiding under vias connected to wide Cu metal leads", IRFS 2002
2. K. Yoshida, et al., "Stress induced voiding phenomena for an actual CMOS LSI interconnects", IEDM 2002
3. T. C. Huang, et al., "Numerical modeling and characterization of the stress migration behavior upon various 90 nanometer Cu/Low interconnects", IITC 2003
4. M. Kawano, et al., "Stress relaxation in dual damascene Cu interconnects to suppress stress-induced voiding", IITC 2003
5. G. Taguchi, S. Chowdhury, S. Tguchi, "Rubust Engineering", McGraw-Hill, published date October 18, 1999
6. A. Kajita, et al., "High reliable Cu/low-k dual damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65nm-node high performance eDRAM", IITC 2003
7. R. Kanamura, et al., "Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65nm node high performance eDRAM", VLSI Symposium 2003