Dynamic fraction control bus: New SOC on-chip communication architecture design

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2005, Pages 199-202

  Wang, Nan ^a   Bayoumi, M A ^a  

^a University of Louisiana at Lafayette   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; INTERNET; NETWORK PROTOCOLS;

COMMUNICATION ARCHITECTURES; STATIC FRACTION CONTROL BUS (SFCB); SYSTEM-ON-A-CHIPS (SOC);

MICROPROCESSOR CHIPS;

EID: 30844432186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. X. Zhu and S. Malik, "A hierarchical modeling framework for on-chip communication architectures", IEEE/ACM international conference on Computer-aided design, p663-p671, 2002
2. "Peripheral integration architecture, Sonics." http://www.sonicsinc.com.
3. "Sonics interconnect bus architecture." http://www.omimo.be.
4. K. Lahiri, A.Raghunathan, G. Lakshminarayana, "LotteryBus: A new high-performance communication architecture for System-on-Chip designs", 38th Conference on Design Automation (DAC'01), p15-p20, 2001.
5. J.Tumer and N.Yamanaka, "Architectural choices in large scale ATM switches," IEICE Trans.on Communications, vol E-81B, Feb 1998.
6. "ATM Overview, ESRF", http://www.esrf.fr/computing/cs/nice/ impl/atm/atm.html