Neural network-based modeling & resign of on-chip spiral inductors

Proceedings of the Annual Southeastern Symposium on System Theory

Volumn 36, Issue , 2004, Pages 561-564

  Ilumoka, A ^a   Park, Yeonbum ^a  

^a UNIVERSITY OF HARTFORD   (United States)

Author keywords

Circuit Optimization; HF Analog 1C's; Modeling; Neural Networks; Spiral Inductors

Indexed keywords

CIRCUIT OPTIMIZATION; MODELING; ON-CHIP SPIRAL INDUCTORS; SPIRAL INDUCTORS;

CAPACITANCE; ELECTRIC INDUCTORS; ENERGY DISSIPATION; EXTRACTION; GEOMETRY; INDUCTANCE; NATURAL FREQUENCIES; OPTIMIZATION; PARAMETER ESTIMATION; SCATTERING; SILICON; SUBSTRATES; WIRELESS TELECOMMUNICATION SYSTEMS;

NEURAL NETWORKS;

EID: 3042831132     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (8)

1. Chao et al., "Characterization and Modeling of On-Chip Spiral Inductors for Si RFICs," IEEE Trans On Semiconductors Man., Vol. 15, No.l February 2002.
2. J. R. Long, "The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RFIC's," IEEE Jour, of Solid-State Circuits, Vol. 32, March 1997.
3. Kenneth O, "Estimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies," IEEE Journal of Solid-State Circuits, Vol. 33, No.8, August 1998.
4. Burghartz et al, "RF Circuit Design Aspects of Spiral Inductors", IEEE Journal of Solid-State Circuits, Vol. 33, No.12, Dec. 1998, pp. 2028-2032.
5. Sundararajan et al, "Simple Accurate Expressions for Planar Spiral Inductances", IEEE Journal of Solid-State Circuits, Vol. 34, No. 10, October 1999.
6. Mohan et al, "Bandwidth extension in CMOS with Optimized On Chip Inductors, ", IEEE J of Solid-State Circuits, Vol. 35, No.3, March 2000, pp. 2028-2032
7. James A. Freeman/David M. Skapura, "Neural Networks Algorithms, Applications & Programming Tech," Addison-Wesley Publishing Company, Inc. 1992
8. Neuralware Inc.,"Neural Computing Technology Handbook", Neuralware Inc., 1996