A comparative study of two Boolean formulations of FPGA detailed routing constraints

IEEE Transactions on Computers

Volumn 53, Issue 6, 2004, Pages 688-696

  Nam, Gi Joon ^a   Aloul, Fadi ^b   Sakallah, Karem A ^c   Rutenbar, Rob A ^d  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b AMERICAN UNIVERSITY IN DUBAI   (United Arab Emirates)

^c The Department of Civil and Environmental Engineering   (United States)

^d Dept of Electrical and Comp Eng ^*  (United States)

Author keywords

Boolean satisfiability; FPGAs; Physical design; Routing

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT;

BOOLEAN SATISFIABILITY; PHYSICAL DESIGN; ROUTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 3042664227     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.1     Document Type: Article

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