Accuracy improvement of the "single pattern driver" method for the characterization of interconnect capacitance in the context of nanometer technology development

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 303-308

  Brut, H ^a   Martin, S ^a   Froment, B ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHARACTERIZATION; DIODES; NETWORKS (CIRCUITS); SEMICONDUCTOR JUNCTIONS;

INTERCONNECT CAPACITANCE; PARASITIC CAPACITANCES;

CMOS INTEGRATED CIRCUITS;

EID: 3042661894     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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6. C.J.Chao, S.C.Wong, M.J.Chen and B.K.Liew, "An Extraction Method to Determine Interconnect Parasitic Parameters", published in IEEE Transactions on Semiconductor Manufacturing, Vol.11, No.4, p.615, 1998.
7. J.C.Chen, D.Sylvester and C.Hu, "An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad Resolution", published in IEEE Transactions on Semiconductor Manufacturing, Vol.11, No.2, p.204, 1998.