Test structure for direct extraction of capacitance matrix in VLSI

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1999, Pages 200-205

  Mido, T ^a   Ito, H ^a   Asada, K ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; INTEGRATED CIRCUIT TESTING;

CAPACITANCE MATRIX; FEMTO-FARAD ORDER; MULTILAYER INTERCONNECTIONS;

VLSI CIRCUITS;

EID: 0032658216     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (2)