A novel test-structure for detail interconnect fabric diagnosis for 90nm process

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 81-86

  Akutsu, Shigekiyo ^a   Ishihara, Noriyuki ^b   Masuda, Hiroo ^a  

^a Semiconduct Technol Acad Res C   (Japan)

^b Fuji Research Institute Corporation   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE MEASUREMENT; CHARACTERIZATION; COMPUTER AIDED DESIGN; DELAY CIRCUITS; DIELECTRIC MATERIALS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; MULTILAYERS; PERMITTIVITY; SIGNAL PROCESSING; STATISTICAL METHODS;

PATTERN DENSITY CONTROL; PERMITIVITY EXTRACTION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 3042658235     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. ITRS 2001 Edition
2. K.Yamada et al. "Accurate modeling method for deep sub-micron Cu interconnects" pp. 111-112, 2003 VLSI Tech. Symposium.
3. S.P.Khatri et al. Cross-talk noise immune VLSI design using regular layout fabrics, Kluwer Academic Publisher, 2001
4. A.Kurokawa et al. "DEPOGIT: Dense Power-Ground Interconnect Architecture for Physical Design Integrity", ASP-DAC2004, to be published.
5. Kanemoto et al. "Interconnects characterization methodology for 90nm level SoC processes", DA Symposium 2003, pp231-236.
6. S.Okawa et al. "Analysis and characterization of device variations in an LSI chips using an integrated DMA", ICMTS2003, pp.70-75.
7. K. Akutsu et al. "Simulation Technology for ILDEx," DA Symposium 2002, pp211-216.
8. Hashimoto et al. "ILDEx test structure and their field solver simulation for interconnects thickness estimation", System LSI Workshop 2001.