Accurate Modeling Method for Deep Sub-Micron Cu Interconnect

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 111-112

  Yamada, K ^a   Okada, N ^a   Yasuda, M ^a   Oda, N ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ETCHING; INTEGRATED CIRCUIT LAYOUT; SPUTTERING; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT INTERCONNECTS;

LAYOUT PARAMETERS EXTRACTION (LMP);

ELECTRIC CONNECTORS; EXTRACTION;

ACCURATE MODELING; COPPER INTERCONNECTS; CU INTERCONNECT; DEEP SUB-MICRON; DEEP-SUB MICRONS; LAYOUT DENSITIES; LAYOUT PATTERNS; MODEL METHOD; TEST PATTERN; THICKNESS DEPENDENCE;

EID: 0141426810     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. S. Takahashi et al., Tech. Dig. IEDM, 1998, p.833.
2. Qing-Tang Jiang et al., Proc. of IITC, 2001, p.227.