Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems

Proceedings - 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1996

Volumn , Issue , 1996, Pages 164-174

  Kol, R ^a   Ginosar, R ^a   Samuel, G ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC;

ASYNCHRONOUS DESIGN; ASYNCHRONOUS SYSTEM; CAD TOOL; MULTIPLE LEVELS; NOVEL METHODOLOGY; STATECHARTS; SUB-SYSTEMS;

COMPUTER AIDED DESIGN;

EID: 61749100811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1996.494448     Document Type: Conference Paper

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