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Volumn 2, Issue , 2004, Pages 1368-1369

From synchronous to asynchronous: An automatic approach

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CONTROLLERS; DE-SYNCHRONIZATION; FLOW EQUIVALENCE; SYNCHRONOUS CIRCUITS; ASYNCHRONOUS CIRCUITS; AUTOMATIC APPROACHES; CLOCK DISTRIBUTION; POTENTIAL BENEFITS;

EID: 3042565270     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269092     Document Type: Conference Paper
Times cited : (13)

References (5)
  • 1
    • 2942669979 scopus 로고    scopus 로고
    • A concurrent model for de-synchronization
    • Extended version of paper presented at
    • J. Cortadella, A. Kondratyev, L. Lavagno, and C. Sotiriou. A concurrent model for de-synchronization. Extended version of paper presented at IWLS03. www.Isi.upc.es/~?jordicf/publications/pdf/iwls03-extended.pdf.
    • IWLS03
    • Cortadella, J.1    Kondratyev, A.2    Lavagno, L.3    Sotiriou, C.4
  • 4
    • 0030244752 scopus 로고    scopus 로고
    • Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry
    • Sept.
    • D. H. Linder and J. C. Harden. Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry. IEEE Transactions on Computers, 45(9):1031-1044, Sept. 1996.
    • (1996) IEEE Transactions on Computers , vol.45 , Issue.9 , pp. 1031-1044
    • Linder, D.H.1    Harden, J.C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.