Tight area upper bound for slicing floorplans

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 280-285

  Peixoto, Helvio P ^a   Jacome, Margarida F ^a   Royo, Ander ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GEOMETRY; NUMERICAL ANALYSIS; NUMERICAL METHODS; OPTIMIZATION;

SLICING FLOORPLANS; UPPER BOUND;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033876211     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)